Assistant Design

Yi-Chung Chen

Name: Yi-Chung Chen

C ONTACT

I NFORMATION Mobile: +1-347-***-****

Email: *******.****.**@*****.***

Address: **** ******** **. **********, ** 15217, USA

Highest Degree: Ph.D (with GPA 3.875/4) (Graduation: 06/30/2014)

Nationality: Taiwan

Reconfigurable Computing: FPGA, PR, Security, HPC

P ROFESSIONAL

B ACKGROUND Memory Technology: RRAM, FLASH, PCM, STTRAM, Sensing, Reliability

Computer Aided Design: Placer, Router, VPR, Power Estimation

System Design: High Speed Interface, BOM, Analog Circuit, Power, Firmware, PCB

VLSI Design: Custom, ASIC, Layout, Digital Circuit, RTL, Timing, SOC, Power

Advanced Nano Device: sub-30nm MOS, FinFet, Process, Leakage Current

EDA tools: HSPICE, PSPICE, Cadence Virtuoso, Cadence RTL Compiler, Cadence SOC

P ROFESSIONAL

S KILLS Encounter, Synopsys Design Compiler, Modelsim, Synopsys TCAD (Medici and Taurus),

TINA (TI), Allegro.

Other software: Xilinx ISE, Altera Quartus II, Matlab, VPR/VTR for FPGA.

Programming language: C/C++, VHDL, Verilog, Verilog-A, Perl, Python, System Verilog.

University of Pittsburgh, Pittsburgh, PA, USA

E DUCATION

Doctor of Philosophy Sep. 2012 – Summer, 2014

• Major: Electrical and Computer Engineering

• Advisor: Professor Hai (Helen) Li

New York University, Brooklyn, NY, USA

Doctor of Philosophy Jan. 2010 – Aug. 2012

• Major: Electrical and Computer Engineering

• Advisor: Professor Hai (Helen) Li

Stony Brook University, Stony Brook, NY, USA

Doctor of Philosophy Sep. 2009 – Dec. 2009

• Major: Electrical and Computer Engineering

Yuan Ze University, Taoyuan, Taiwan

Bachelor of Science Sep. 2002 – Jun. 2006

• Major: Electrical Engineering (Nanotechnology)

• Advisor: Professor Chun-Hsing Shih

Texas Instruments, Taipei (Asia site), Taiwan

W ORK

E XPERIENCE Technical Support Engineer Sep. 2008 – Jul. 2009

( FULL TIME )

• High Performance Analog (HPA), High Volume Analog and Logic (HVAL)

Circuit Design; Design Verification; Customer Support;

University of Pittsburgh, Pittsburgh, PA, USA

R ESEARCH

EXPERIENCE

Research Assistant: Sep. 2012 – Summer, 2014

• RRAM FPGA in security application:

Operation of RRAM FPGA for high level security applications;

• CAD tool for Partial Reconfiguration Hardware:

Physical synthesis for partial reconfiguration on FPGA;

Hierarchy power estimation for FPGA;

• Heterogeneous Computation:

Partial reconfiguration from VPR to FPGA board;

General PC/Workstation platform with FPGA Accelerator;

Nanyang Technological University, Singapore, Singapore

Research Assistant: Jun. 2013 – Sep. 2013

• CAD tools for partial run-time reconfigurable FPGA:

A nano/CMOS hybrid Dynamically Reconfigurable Embedded System Platform and

Mapping Flow;

New York University, Brooklyn, NY, USA

Research Assistant: Jan. 2010 – Aug. 2012

• Design and Analysis of 3D Stacking Crossbar RRAM:

High density interleaved structure for crossbar RRAM;

Performance analysis and design space exploration of various RRAM device in stacking

crossbar;

• Peripheral Circuit Design for Crossbar RRAM in Lookup table:

High speed sensing scheme for crossbar RRAM on extended array;

Design space exploration of crossbar RRAM in sensing and writing scheme;

• RRAM FPGA and unified-BRAM (uBRAM) FPGA:

Crossbar RRAM in nonvolatile memory FPGA;

Circuit design of RRAM FPGA in routing elements;

Reconfigurable operation with fast uBRAM FPGA for fast loading reconfigurable FPGA;

Reconfigurable schemes with uBRAM FPGA;

Yuan Ze University, Taoyuan, Taiwan

Research Assistant: Jan. 2004 – Dec. 2006

• Sub-30nm Schottky Barrier CMOS:

Project is funded by National Science Council for Yi-Chung Chen (Student) and Chun-

Hsing Shih (Advisor);

Device design of sub-30nm Schottky Barrier MOS;

• Trainee in National Nano Device Lab (Taiwan):

Fabrication of Schottky Barrier device;

• Miscellaneous Projects of Digital and Analog Circuit Design

Y.-C. Chen, W. Zhang, and H. Li, “A Hardware Security Scheme for RRAM-based FPGA,”

C ONFERENCE

P UBLICATIONS in IEEE International Conference on Field Programmable Logic and Applications (FPL),

2013, pp. 1–4.

Y.-C. Chen, W. Wang, W. Zhang, and H. Li, “uBRAM-based Run-time Reconfigurable FPGA

and Corresponding Reconfiguration Methodology,” in IEEE International Conference on

Field-Programmable Technology (FPT), 2012, pp. 80–86.

Y.-C. Chen, W. Wang, H. Li, and W. Zhang, “Non-volatile 3D stacking RRAM-based FPGA,”

in IEEE International Conference on Field Programmable Logic and Applications (FPL),

2012, 367–372.

Y.-C. Chen, H. Li, and W. Zhang, “A Novel Peripheral Circuit for RRAM-based LUT,” in

IEEE International Symposium on Circuits and Systems (ISCAS), 2012, pp. 1811–1814.

Y.-C. Chen, W. Zhang, and H. Li, “A Look Up Table Design with 3D Bipolar RRAMs,” in

IEEE Asia and South Pacific Design Automation Conference (ASPDAC), 2012, pp. 73-78.

Y.-C. Chen, H. Li, W. Zhang, and R. E. Pino, “3D-HIM: A 3D High-density Interleaved

Memory for Bipolar RRAM Design,” in IEEE/ACM International Symposium on Nanoscale

Architectures (NANOARCH), 2011, pp. 59–64.

Y.-C. Chen, H. Li, Y. Chen, and R. Pino, “3D-ICML: A 3D Bipolar ReRAM Design with In-

terleaved Complementary Memory Layers,” in IEEE Design, Automation & Test in Europe

Conference & Exhibition (DATE), 2011, pp. 1–4.

S.-P. Yeh, C.-H. Shih, Y.-C. Chen, Y.-F. Chen, and W.-F. Wu, “Design considerations of Schot-

tky barrier source/drain MOSFETs,” Symposium on Nano Device Technology (SNDT),

2008, pp. 31–32.

Y.-C. Chen, H. Li, W. Zhang, and R. E. Pino, “The 3D Stacking Bipolar RRAM for High

J OURNAL

P UBLICATIONS Density,” IEEE Transactions on Nanotechnology, pp. 948–956, 2012.

More coming soon.

F. Mao Y.-C. Chen, W. Zhang, and H. Li, “BMP: A Fast B*-Tree based Modular Placer for

C ONFERENCE

P OSTERS FPGAs,” in ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

(FPGA), Feb. 2014, pp. 248–248.

H. Liang Y.-C. Chen, W. Zhang, and H. Li, “Hierarchical Library Based Power Estimation

for Versatile FPGAs,” in ACM/SIGDA International Symposium on Field-Programmable

Gate Arrays (FPGA), Feb. 2014, pp. 243–243.

Y.-C. Chen, H. Li, W. Zhang, and R. E. Pino, “A RRAM-based Memory System and Appli-

W ORKSHOP

P UBLICATIONS cations,” in Non-volatile Memory Workshop (NVMW), Mar. 2012.

Travel grants: Non-volatile Memory Workshop (NVMW), 2012.

H ONORS AND

AWARDS

Full scholarship with stipend of New Century Leader (NCL) program: Yuan Ze Univer-

sity, Sep. 2002 – Jun. 2006.

PR-aware router for FPGA (VPR): PR-aware router for partial reconfiguration FPGA. (In-

R ELEASING

M ODELS AND tegration with VPR 6)

T OOLS

Neuron Network Clustering and Optimization tool: Physical synthesis of neuron network

with clustering and optimization for synapse model reduction.

Hierarchy Library based Power Estimation for FPGA (VPR): Power estimation tool with

hierarchy power model and physical parameters. (Integration with VPR 6)

B*-tree based modular placer for FPGA (VPR): Fast B*-tree modular placer supporting

pre-synthesized logic modules. Netlist combination tool is included in the tool. (Integration

with VPR 6).

3D-HIM SPICE model generator: High density crossbar netlist with Bi-group operation

for SPICE simulation with interconnection model, including resistance, capacitance.

Crossbar SPICE model generator: Crossbar netlist for SPICE simulation with interconnec-

tion model, including resistance and capacitance.

RRAM switching model: Compact verilogA model of RRAM for fast simulation.

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