ASIC Design and Verification Engineer

Ramesh Narayana Reddy L

(Fresher ASIC Design & Verification Engineer)

Bangalore

Contact # +91-810*******

Email: **************@*****.***

Career Objective

Quest to work in real professional atmosphere that enables me to cope-up with the emerging as well

as the latest technology in the field of VLSI and scope for widening the spectrum of my knowledge that

adds value to the company I work for.

Technical Skills

HDL’s : VHDL, VERILOG HDL.

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Tools : MATLAB, Xilinx ISE, ACTIVE HDL, MICROWIND, DSCH, QUESTASIM.

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Clear concepts on DFT, STA, Physical Design, C-MOS Technology, Layout Design and Schematic Drawing

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Knowledge on the Basics of Scripting language Perl.

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Educational Background

BOARD OF YEAR OF PERCENTAGE OF

COURSE INSTITUTE

EDUCATION PASSING MARKS

B.Tech RGMCET, Nandyal, AP JNTU 2014 71.15%

Narayana Junior College, B.I.E

Intermediate 2009 92.00%

Hyderabad, AP Andhra Pradesh

Ushodaya High School, Proddatur, State board of

S.S.C 2007 84.33%

AP Andhra Pradesh

Project Experience

1. High Performance Hardware Implementation of AES using minimal resources .

Description: Hardware implementations of cryptographic algorithms are physically secure than

software implementations since outside attackers cannot modify them. In order to achieve higher

performance in today’s heavily loaded communication networks, hardware implementation is a wise choice

in terms of better speed and reliability. In order to achieve higher speed and lesser area, Sub Byte operation,

Inverse Sub Byte operation, Mix Column operation and Inverse Mix Column operations are designed as

Look Up Tables (LUTs) and Read Only Memories (ROMs).

2. UART Protocol Design and Verification.

Description: A UART is usually an individual integrated circuit used for serial communications

over a computer or peripheral device serial port. UART’s are now commonly included in microcontrollers.

The UART takes bytes of data and transmits the individual bits in a sequential fashion . Here successfully

designed the Verilog code and verified the output and the power constraints.

3. Layout design for 4 X 4 Vedic multiplier.

Description: Multiplication is one of the more silicon-intensive functions, especially when

implemented in Programmable Logic. Multipliers are key components of many high performance

systems such as FIR filters, Microprocessors, Digital Signal Processors, etc. Here implemented the

layout for 4 X 4 multiplier and fixed all the DRC Violations, Verified the simulation results. Analyzed the

Power, Area and Delay parameters.

Certifications and Professional Trainings

Diploma in ASIC Design and Verification from NANO Scientific Research, Hyderabad.

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Undergoing Functional Verification using System Verilog and Methodologies at CVC Bangalore.

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Extra Curricular Activities

Awarded for 1st prize in district level Quiz competitions in the years 2002 & 2004

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Organized EVINCE 2K10 & 2K12 presided by our department.

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Organized RGM-SANGRAM intercollegiate sports fest in 2K12 & 2K13.

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Participated in National Service Scheme programs and planted trees.

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Organized EXPO 2K12 a student managed trade fair presided by our college.

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Personal Identity

Father’s Name : L Sudhakar Reddy

Sex : Male

Date of Birth : 24-07-1991

Religion : Hindu

Marital Status : Single

Mailing Address : 7/527-2, Y.M.R Colony, Proddatur, Andhra Pradesh - 516360

Known languages : English, Telugu, Hindi (Read, Write & Speak)

Declaration

I hereby declare that the above information furnished in my curriculum vitae is true to the best of my

knowledge.

Date:

Place: Bangalore L.RAMESH NARAYANA REDDY

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