VLSI

VIKRAM SHANMUGA SUNDARAM

**** ********* ******, #* ********@****.**.***

Cincinnati, OH 45220 513-***-****

EDUCATIONAL QUALIFICATIONS

The University of Cincinnati CGPA: 3.3/4

December ’14

Master of Engineering in Electrical Engineering

Anna University, India CGPA: 7.8/10

June ’13

Bachelor of Engineering in Electrical Engineering

Coursework: VLSI Physical Design, Computer Architecture, VLSI Design Automation, VLSI Testing

& Low Power Design, MEMS, Effectiveness in Technical Organizations.

Availability: August 2014 onward. Visa Status: F-1

TECHNICAL SKILLS

Simulation Tools: HSPICE, PSPICE, IRSIM, Synopsys VCS, ModelSim, LTspice

Layout Editor: MAGIC

Hardware Description Languages: Verilog, VHDL

Programming Languages: Data Structures and Algorithms using C and C++

Scripting Languages: Perl

EDA Tools: Synopsys Design Compiler (BSD Compiler, DFT Compiler, Power Compiler), Tetramax

Operating Systems: Windows, Linux/Unix, MacOS

ACADEMIC PROJECTS

Practical chip design of a stream cipher:

RTL design of a stream cipher in Verilog followed by simulation in ModelSim.

Designed a 156 bit stream cipher using a programmable LFSR scheme in CMOS 0.3µm using

MAGIC layout editor.

Design focused on maximizing the number of bits and achieved an area utilization of 95% with

a frequency of 100MHZ.

Included scan chains for testing. Post fabrication chip testing used a 16902A Logic Analyzer.

Placement and Routing tool in Design Automation using C++:

Placement was performed using the forced directed algorithm, routing used Lee’s multilayer

maze routing algorithm.

Design focused on minimizing area and reducing run time, achieved 100% routing for the

highest benchmark within 2 minutes.

Design, Synthesis, DFT and BSD of a GCD machine:

RTL design of GCD in Verilog, synthesis and scan chain design using Design Compiler

ATPG used Tetramax which achieved 99.86% fault coverage.

Also included an IEEE 1149.1 compliant TAP controller design and synthesis.

Dual Level Power Estimation and Gate Level Optimization:

Power estimation at RTL level and gate level based on the switching activity of a GCD

machine.

Optimization of power at logic level with design constraints was performed at multiple

thresholds.

Balanced Bi-partitioning tool in Design Automation using C++:

Used Simulated Annealing algorithm to perform balanced bi-partitioning of net-lists.

Achieved an optimal cut-set of 2725 while running a benchmark netlist of 45000 nodes and

450000 nets.

HSPICE Power Analysis:

Designed and analyzed an inverter for various power consumption [Leakage, Short

Circuit, Dynamic and Average Power] using different power sources.

Placement and Routing of a GCD Machine:

Process involved creation of Milkyway database, floorplanning, placement, routing and

generation of area, power, timing and clock tree reports using the Synopsys IC Compiler.

A Primary Side Control Scheme for LED Driver:

Designed and fabricated a control mechanism for power aware Light-emitting diode (LED)

enabler.

ACHIEVEMENTS:

Recipient of the University Graduate Scholarship at the University of Cincinnati.

Accomplished debater at the REC-Debating Union.

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