Project Engineering

T.R.ASIF

E-mail: acfku5@r.postjobfree.com

Ph. no: +91-970*******

CAREER OBJECTIVE:

To work in an environment that would challenge my abilities and offer me

professional growth while being innovative and contributing to the growth of

your organization.

ACADEMIC PROFILE:

Course

Discipline

School/College

Board/University

Course period

Percentage

M.TECH

VLSISD

JNTU

JNTU,ANATAPUR

2013-2015

82.3*

B.E

ELECTRONICS AND

COMMUNICATION

Sir C R Reddy College Of Engineering

Andhra University

2012

8.11(CGPA)

Intermediate

MPC

Aditya Junior College

Board Of Intermediate Education

2006-2008

94.40

10thclass

SSC

Flora E.M. High School

Board Of Secondary Education

2005-2006

92.5

SKILLS:

LANGUAGES : C basics, RTL coding (VERILOG), Perl, Python scripting

SYSTEM VERILOG basics

Tools : VCS, HSPICE, Design Compiler (synthesis),IC

Compiler(physical design flow i.e. floor planning, placement, clock tree

synthesis, routing)

ACADEMIC PROJECTS:

Project: Designing of CARRY SAVE ADDER,SHIFT REGISTERS, FIFO

Language: VERILOG

Tools used: VCS, DC (Synopsys)

Project Description:

Carry save adder : A carry-save adder is a type of digital adder, used in

computer micro architecture to compute the sum of three or

more n-bit numbers in binary. It differs from other digital adders in that it

outputs two numbers of the same dimensions as the inputs, one which is a

sequence of partial sum bits and another which is a sequence of carry bits.

Shift Register: In digital circuits, a shift register is a cascade of flip

flops, sharing the same clock, in which the output of each flip-flop is

connected to the data input of the next flip-flop in the chain, resulting in a

circuit that shifts by one position the bit array stored in it, shifting

in the data present at its input and shifting out the last bit in the array, at

each transition of the clock input.

FIFO: FIFO is a method of organizing and manipulating a data buffer, where the

oldest entry or head of the queue is processed first. FIFO primarily consists

of asset of read and write enable pointers, storage and control logic. An

asynchronous FIFO uses different clocks for reading and writing. A synchronous

FIFO is a FIFO where the same clock is used for both reading and writing. Data

presented at the module data in is written in to the next available memory

location on a rising clock edge. Data can be read out via modules data output

port in the order in which it was written by asserting read enable. In my

design I implemented the synchronous FIFO

The RTL(VERILOG) code were written for the above designs which were compiled

and simulated using Synopsys Verilog Compiler Simulator (VCS) to observe the

schematic and waveforms and the same designs are synthesized by 90nm

technology using Design compiler (DC) and generated optimized gate level

netlist

B.E PROJECT:

Mini projects : Model Railway Level Crossing Lights, Real Time Operated

Industrial Loads

Main project : Speaker Recognition Using MFCC

Project Description: Speaker recognition is part of speech recognition, it is

not the purpose of identifying what the speaker is talking about, but who is

the speaker. This project presents a security system based on speaker

verification. Mel Frequency Cepstral Coefficients (MFCC) is used for feature

extraction. A particular speaker utters a password once in the training session

so as to train and store the features. Later in the testing session the user

utters the password again in order to achieve recognition if there is a match.

ACHIEVEMENTS:

. Recipient of GBK merit scholar award for best performance in

Intermediate .

. Recipient of merit award by Viswa Sai cultural organization for best

performance in SSC

. Won first prize in Technical Quiz conducted by IETE forum in

engineering.

. Won second prize in General Quiz conducted by IETE forum in

engineering.Participated in Project Exhibition organized in Andhra

University.

CO-CURRICULAR ACTIVITIES:

. Presented technical papers on DIGITAL SIGNAL PROCESSING in

Guntur Engineering college and Loyola institute of technology,

Guntur .

. Mini Projects exhibited in Tech -fest organized by Sir C R Reddy

Engineering college.

. Participated as a volunteer in NSS blood donation camp organized

in Sir CRR Engineering college.

PERSONAL TRAITS:

. Positive attitude, willingness to learn and belief in hard work.

. Dedication with an inner drive to succeed and accomplish goals.

. Adapt to changes quickly while doing any work.

PERSONAL PROFILE:

Name : Thotallo Rompicherla Asif Basha

Gender : Male

DOB : 04-08-1991

Address : D.no:10-262, Vuyyuru -521165, Krishna

dist, A.P

Fathers name : T.R. Khader Basha

Hobbies : Listening music, solving puzzles.

Languages known : Urdu, Telugu, Hindi and English.

Religion : Muslim

Nationality : Indian

Declaration:

I

do hereby submit that all the information provided is true and correct to

the best of my knowledge.

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