Design Engineering

DHAVAL AGRAWAL

CELL NO.: +91-972******* E-MAIL ID:

******.*********@*****.**

OBJECTIVE

• Looking for opportunity where I can add values to organization & myself through conceptual

application of my classroom teaching & technical skills.

• To be self-motivated next generation technocrat with the ability to adapt to rapidly changing

technologies and environments with a strong desire to understand challenging tasks to work with

the team to achieve the organization goals.

ACADEMIC QUALIFICATION

Percentage

Degree Year /CPI/CGP School/College Board/University

A

Laljibhai Chaturbhai

M.E. 8.03

2014 Institute of Technology, Gujarat Technology University

(VLSI) CPI

Bhandu

Government Engineering

B.E. 7.19

2012 College Sec-28, Gujarat Technology University

(E.C.) CGPA

Gandhinagar

Shri J M Chaudhary Gujarat Secondary & Higher

H.S.C. 2008 76.80 % Sarvajanik Vidyalaya, Secondary Education Board,

Mehsana Gandhinagar

Shri Vardhaman Vidyalaya, Gujarat Secondary Education

S.S.C. 2006 86.43 %

Mehsana Board, Gandhinagar

CORE COMPENTENCY

• Good knowledge of Digital Logic Design

• Basic knowledge of transistors fundamentals and CMOS Fabrication process

• Good understanding of ASIC design flow and FPGA design flow

• Good understanding of Testing and verification and Layout Design

• Working knowledge of Linux Commands

• Have basic knowledge of Analog VLSI design concepts

• Basic knowledge of Antenna and Wave propagation, microprocessor

• Basic knowledge of Data communication and Networking

• Good Management, personal & organizational skills

TOOLS USED

Mentor Graphics EDA tools : Eldo, IC Studio

Xilinx Inc. : Xilinx ISE, ModelSim

Tanner EDA Inc. : T-SPICE

Hardware Description Language : VHDL

Programming Languages : C,HTML

Operating Systems : Windows (7, XP, VISTA), LINUX

Others : Matlab, Microwind, Multisim

ACADEMIC PROJECTS

1. Designing of Standard Cells

• Tools Used: Eldo, IC studio and calibre from Mentor Graphics

• Description: SPICE design, schematics and layout of standard cells like NAND, NOR, Flip-

flops etc. Also verify DRC, LVS and PEX for this cell.

Using this standard cell multiplexer, half adder etc. are also implemented

2. NAND gate using Multiplexer

• Tools Used: Xilinx, Modelsim, IC studio and calibre from Mentor Graphics

• Description: Implemented RTL of NAND gate by use of multiplexer using VHDL and

design is verified with VHDL test bench. Also schematic driven layout generated and verified

for DRC and PEX.

Further, using multiplexer NOR gate and D-FF also implemented.

3. Comparator Based Switched Capacitor Circuits

• Tools Used: Eldo, IC studio from Mentor Graphics

• Description: In this project, I have designed Comparator Based Switched Capacitor Circuits

in 90nm CMOS technology. Also noise analysis is done in this circuit. MOS switches,

comparator and non-overlapping clocks are main building blocks. The accuracy is dependent

on the accuracy of comparator and also comparator is major source of noise in this circuit.

STRENGHTS

• Interested in rapid change in technology

• Good knowledge of technical subjects

• Ability to work as team member and can adjust in any environment

• Good designing and problem solving skill

ACHIEVEMENTS

• Qualified in GATE 2012 with score of 314.

PERSONAL DETAILS

Name

Date Of Birth

Languages Known

Present Address

Permanent Address

Nationality

Goal

DECLARATION

I hereby declare that all the particulars mentioned above are true to the best of my knowledge and

I bear the responsibility for the correctness of above particulars.

Place: Pune

DHAVAL AGRAWAL

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