Design Engineer

CURRICULAM VITAE

Kiran Babu. N

Email:*****.********@*****.***

D.NO.#69/9,indhraNilaym, Contact no: +91-738*******

Muniappa Layout, Hong Sondra layout +91-805*******

G.B.Palya, Hosur Main road

Bangolore-68

CAREER OBJECTIVE

To constantly explore new horizons & achieve higher goals, pursuing a challenging career and

as an integral member of the organization, enhance business growth. With a positive attitude I

would like to broaden & develop my skill while contributing to the corporate productivity &

performance.

AREAS OF KNOWLEDGE

• Experience in Analog Layout Designing (Floor planning, DRC and LVS).

• Knowledge in Analog layout Design or Custom Layout Design.

Cells designed for Decoders, Inverters, flip-flops and latches by using Cadence tool.

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Physical implementation of the Functional blocks in ASIC flow

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Good understanding of the ASIC and FPGA design flow

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Very good knowledge in verification methodologies

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Experience in using industry standard EDA tools for the front-end design and verification

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VLSI DOMAIN SKILLS

HDLs: Verilog and VHDL

HVL: System Verilog

EDA Tool: Modelsim and ISE, Questa, Cadence tool

Domain: ASIC/FPGA Design Flow, Digital Design methodologies

Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Functional Coverage, Synthesis.

Languages: C, C++.

Cadence : Virtusa, Assura, Encounter.

Physical Design: Cadence Virtuoso (Full Custom Design).

PROFESSIONAL QUALIFICATION

• Maven Silicon Certified Advanced VLSI Design and Verification course

from Maven Silicon VLSI Design and Training Center, Bangalore Year: oct 2012.

CADENCE TOOLS:

Experience in Custom layout designing 45nm technology using cadence tools.

• Encounter

• Cadence Virtuoso L and XL editor

• Assura - DRC & LVS

Technology: 90nm, 45nm.

EDUCATIONAL PROFILE

• Master in VLSI Design at KL University Vijayawada in 2013 with 8.7 CGPA.

• Bachelor of Science in Electronics at L.B.R.C.E Vijayawada in 2011.

• Diploma in Electronics at G.I.O.E Secunderabad in 2008.

• SSC in 2004.

VLSI PROJECTS

Physical Coding Sublayer (PCS) – RTL design and Verification

Cadence Tools: Virtuoso Layout Editor, Assura, Encounter.

HDL: Verilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

Description: Physical coding Sublayer (PCS) of 1000BASE.X, which performs 8bit/10bit

encoding and decoding respectively, has to be designed and verified using Verilog HDL. This is

one among the three Sub layers of the physical layer. This plays a significant role in Ethernet.

Implemented the RTL using Verilog HDL

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Verified the RTL using Verilog HDL

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Implemented the design on the Spartan, Xilinx FPGA and verified the design on the

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board

Layout designed for the project and we calculating the power dissipation, area by using

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of Cadence tool.

MAIN PROJECT (B. Tech)

• Modification of least mean square equation error algorithm for IIR system Identification & Adaptive filtering.

MAIN PROJECT (Diploma)

• Point to multipoint wireless communication with remote switching.

AREA OF INTEREST

• Digital Circuits & Logic Design

Introduction to C-MOS & Basic VLSI design

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CMOS VLSI Design (Analog/Digital)

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• ASIC Design, RTL Design,

• Physical Design and Verification.

• FPGA Design.

ADDITIONAL INFORMATION

• Design and development of various HDL modules using Xilinx Spartan-3E FPGA board.

• Xilinx FPGA board programming using ISE, EDK.

• Design logic level and physical layout verification using Microwind.

PERSONAL INFORMATION

Name : Nuthalapati Kiran Babu

Father’s Name : N.Devadasu

Date of Birth : 10-07-1989

Gender : Male

Marital Status : Single

Hobbies : Dancing and Cricket

Nationality : Indian

DECLARATION

The above achievements are a measure of my sincerity and capability to work in teams

and successfully execute any enterprising work. With the right combination of your needs and

my capabilities, I trust that we can achieve the goal.

Date: Bangalore

Place: 28-07-2014

Kiran babu.N

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