RTL, Verilog, FPGA/ASIC Design, Emulation, FPGA Bring up, Lab tools.

RESUME of ANIRBAN MOITRA (Msc-IC Design)

: ANIRBAN

First Name

: MOITRA

Surname

Profile Snapshot:

- Experience of 10 years (including Masters of 18 months) in FPGA/ASIC design and RTL coding.

- Worked on synthesizable VIPs/Transactors running on Emulation boxes (Veloce, Palladium,

Zebu, etc).

- Have led multiple teams of over five members each simultaneously.

- Done IP Validation on FPGA on prototype boards.

- Used Xilinx ISE and Altera Quartus 9.2 and few more EDA tools.

- Hands on experience with hardware debugging tools like Xilinx Chipscope, Logic Analyzer, CRO

etc.

- Worked on IEEE 1394 (Firewire), NAND Flash Controller, SDIO Host and Device and AMBA AHB,

AXI, ACE, OCP, BVCI standards.

EDUCATION

Masters in Integrated Circuit Design from German Institute of Science and Technology

(GIST), Singapore. It is a course offered jointly by Technical University of Munich (TUM), Germany and

Nanyang Technological University (NTU), Singapore.

Bachelor of Engineering from Birla Institute of Technologies, Ranchi, INDIA, in Electrical and Electronics

Engineering, in 2004.

WORK EXPERIENCE

– Working with Synopsys India Pvt Ltd as Manager, R&D.

September 2011 – till date

Responsibilities: Manage and lead the project for Synthesizable Transactor Verification IP development

VIP development of AMBA Protocols: AHB, AXI, ACE.

Lead team of 7.

Develop Transactor architecture that can run on all emulation boxes.

RTL Design and Coding in Verilog. Synthesis and debug on hardware emulator.

Manage, resolve issues and enhancement requests onsite at customer end

September 2010 – August 2011 – Worked with nSys Design Systems as Team Lead.

(Acquired by Synopsys)

Responsibilities: Manage and lead the project for Synthesizable Transactor Verification IP development

VIP development of AMBA Protocols: AHB, AXI.

Lead team of 5.

Develop Transactor architecture that can run on all emulation boxes.

RTL Design and Coding in Verilog. Synthesis checks.

Manage, resolve issues and enhancement requests onsite at customer end.

– Worked with Aizyc Technology, INDIA as ASIC Design

June 2009 – August 2010

Engineer.

Responsibilities: Design IPs on SDIO 2.0 and 3.0 host and device controller

Onsite assignment for Synthesis and STA for Custom FPGA design on Altera Stratix IV.

Bring up IP and design on FPGA prototype board and verify and debug on real time.

Split ASIC design into 16 FPGAs for prototyping and design the on board interfaces

between FPGAs

– Internship and master thesis work at Institute for

June 2008 – Feb 2009

Microelectronics & Mechatronics Systems gGmbh

(IMMS), Ilmenau, Germany

Responsibilities: Bring up the FPGA on IEEE1394 (Firewire) with adding the device driver on x86

processor.

– Masters Studies in Nanyang Technological University,

August 2007 – May 2008

Singapore (MSc in IC Design)

– Worked with Wipro Technologies, INDIA, as senior

July 2004 – July 2007

engineer

Responsibilities: Own the IP on IEEE1394 (Firewire).

RTL Design. Synthesis, P&R on Xilinx ISE.

FPGA bring up on prototype board

BRIEF DESCRIPTION OF TOOLS HANDLED

Hardware RTL Design, Verification, IP Validation on FPGA. Simulation

Acceleration, Synthesizable Transactors

Emulation Veloce, Palladium, Zebu, Transactor coding

OS Unix, Linux, Windows

Languages Verilog, VHDL.

Knowledge of C, C++, SV

Tools/Utilities Verilog XL, NC Verilog, NCSIM,

Synplify-Pro (FPGA Synthesis), Synopsys Design Compiler

(ASIC Synthesis), SimVision, DVE, Verdi,

Atrenta Spyglass (Linting), IUS HAL (Linting)

Xilinx ISE Tools. Chipscope Agilent Logic Analyzer,

Altera Quartus II, Altera AXD Debugger,

Firespy (IEEE 1394 specific),

BRIEF DESCRIPTION OF PROJECTS HANDLED

- Lead the ACE and ACELite Transactor Development for ZEBU

o Team of 7

o Development of Transactor for C++/SV-UVM/TLM-2 Interfaces.

- Lead and architect the development of Simulation Acceleration VIP for AHB,QSB AXI & QSB AHB

o Team of 7

o Architecture to work on all emulation platforms.

o Support for only SV-OVM/UVM Interface

o Full provision for adding TLM-2 and C++ interface

- RTL design and coding of various IPs

o SDIO 2.0, 3.0 Device and Host Controller (With FPGA Prototyping)

o I2C Host controller (With FPGA Prototyping)

o Part of H.264 Video codec

- Timing Analysis and Solution

o ExpressEther bring up on Altera FPGA

o Included bringing up ASIC RTL on FPGA

- FPGA Routing for JPEG2000 (J2K)

o Did the FPGA to FPGA Routing with Mux-DeMux

- Module lead for IP on IEEE1394 (Firewire)

o Develop the RTL and add DMA Engine on the backend interface

o Bring up on FPGA Prototype board

EXTRA CURRICULAR ACTIVIES AND ACHIEVEMENTS

• Participated in National Level School Games in Swimming.

• Was the School Captain.

• Was elected as the Vice Chairperson for IEEE student’s chapter in the University.

• Played football at the University level.

• Led the Wipro Technologies Football team and Basketball team for three years in Inter

Corporate Tournaments.

• Was active member in the Wipro Technologies Cricket team.

• Won the technical paper presentation in VLSI domain and Debate competitions in Wipro

Technologies.

• Reached quarter finals in intra university table tennis tournament in TU Ilmenau, Germany

• Played in the 9 a side soccer tournament organized by Nor-Cal athletics in California, USA

PERSONAL DETAILS

Nationality: Indian

Date of birth: 3rd Aug 1982

Email: ******.*******@*****.***

Phone: +91-965*******, +91-11-423*****

Marital Status: Married

Contact this candidate