ASIC Verification Engineer

Anuj Rawat Mb: 858-***-****

E-Mail: ****.*****@*******.***

LinkedIn: http://in.linkedin.com/pub/anuj-rawat/51/b5a/606

Career Objective

I thoroughly enjoy all aspects of Verification Engineering and the

challenge of dealing with various fields and areas of my job. B.Tech (E&C)

with 1+ yrs of industry experience has allowed me to develop not only my

expertise on Verilog, UVM and System Verilog but also to develop my

communication, problem solving and interpersonal skills through a wide

range of undertaken projects.

Key Skills:

1. 1.5 years of experience in debugging and verification of various

digital systems like UFS 2.0 and USB.

2. Excellent experience in the initialization procedure of UFS 2.0.

3. Experience in IPs having layered architecture.

4. Clear understanding of object oriented programming concept and System

Verilog.

5. Development of IP level Verification platform using System Verilog.

6. Experience in tools like Synopsys VCS and Questa Sim 10.2c.

7. Experience in Perforce Version management.

8. Experience in Verification using methodologies such as UVM and VMM.

9. Experience in debugging System Verilog and Verilog designs.

10. Experience in perl scripting.

11. Excellent problem solving skills, good communication and interpersonal

skills.

Work Experience:

1. Incise Design Services (August-2013 to Present):

Designation: ASIC Verification Engineer.

The role involves:

* Creating the Test spec, Verification Plan, Verification Guide

and Verification Report for the module.

* Preparing a test environment for the UFS 2.0 to be functionally

verified on UVM.

* Preparing required BFMs for the assigned modules (Unipro & UTP)

to test it with the other modules.

* Verification of IP.

* Fixing any issues reported in the assigned module from the

internal testing team.

* Propose a directory structure for the whole project and make a

script for its automation.

2. Nvidia Corporations (February-2013 to August-2013):

Designation: Intern.

The role involved:

* Scripts for automation of Functional Coverage.

* Scripts for running test-cases.

* Fixing any issues reported in the assigned module from the

internal testing team.

* Scripts for test-plan, running regressions and reporting the

results.

Professional Projects:

Project: VIP of UFS 2.0 device (present)

Role: Team Member

Details: Universal Flash Storage (UFS) is a simple, high

performance, mass storage device with a serial interface and has a layered

architecture. UFS Transport Layer (UTP) and MIPI Unipro are two most

important parts of UFS architecture. UniPro is structured as a stack of

protocol layers that roughly follow the OSI Reference Model. UTP is

responsible for encapsulating the protocol into the appropriate frame

structure for the Unipro. The SCSI Architecture Model is used as the

general architectural model for UTP.

Accountabilities and Achievements:

. Thorough understanding of Unipro and UTP Layers.

. Prepare a plan and execute it to make device side

BFMs of them.

. Preparing for the initialization procedure of the

device Unipro and UTP.

. Conducting the UVM RAL method for Unipro's layer's

attributes.

. Creation of verification platform for the testing of

the VIP in UVM.

. Making the interface driver of the device and host of

the project.

. Prepared the directory structure and scripts for the

whole project so as to compile and run the project

automatically.

. Using the TLM connections between the sub layers of

Unipro.

Software Platform/Tools: Questa Sim 10.2c.

Language: System Verilog (UVM), perl.

Project: AUTOMATION OF COVERAGE GENERATION IN USB 2.0 AND USB

3.0 (Nvidia)

Role: Single Member

Details: Functional coverage is a user-defined metric that

measures how much of the design specification, as enumerated by features in

the test plan, has been exercised. Functional coverage ensures that all

desired test cases in the design space have been explored. It tells which

features of RTL have been exercised during random regressions and which are

not. This project was aimed at the automatic generation of various coverage

parameters in USB 2 and USB 3 using perl.

Accountabilities and Achievements:

. Studied thoroughly about the functional coverage and

went through examples.

. Prepared a perl script to parse an excel file and

with it particular format print its coverage

parameters with covergroups and coverpoints in a

system verilog file.

. Hooked the covergroups in the coverage class.

. Running regressions with coverage and reporting it to

the team.

Software Platform/Tools: Synopsys VCS

Language: perl, System Verilog.

Project: VERIFICATION OF ULPI PHY USING VMM (Nvidia)

Role: Team Member

Details: ULPI is an interface standard for high-speed USB 2.0 IP

systems. It defines an interface between USB IP link controllers and the

PHYs or transceivers that drive the actual bus. ULPI stands for UTMI+ low

pin interface and is designed specifically to reduce the pin count of

discrete high-speed USB PHYs.

Accountabilities and Achievements:

. Studied USB 2.0 and ULPI specifications.

. Studied VMM(Verification Methodology Manual)

properly.

. Enhanced the ULPI BFM transactor for emulation test-

bench.

. Debugged the port mismatch problem using VMM.

Software Platform/Tools: Synopsys VCS

Language: System Verilog, Verilog.

Skill Matrix:

. Programming languages : Verilog, System Verilog, Perl,

C++

. Tools Known : Synopsys VCS, ModelSim, Questa Sim

10.2c

. Environment : Windows XP/Windows7, Linux

. Office automation : MS-Office, Open Office

Education:

* August' 2013 : IIIT-Allahabad, B.Tech(Electronics &

Communication) with 7.69 CGPA

* April' 2009 : Senior Secondary Examination with 85%

* April' 2007 : Secondary Examination with 90.6%

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