Electrical Engineer(IIT Patna)

SPANDANA POTINENI

Phone No: +91-924*******

Email id: ********.****@****.**.**,***********.********@*****.***

Academic Details

Year Degree Institute/School,City CPI/%

**** *.****,********** Engineering Indian Institute of 8.33/10

Technology, Patna

2010 Intermediate Education Sri Chaitanya Junior college, 95

Board(XII),Andhra Pradesh Vijayawada

2008 Board of secondary New Era School,Khammam 89.16

education(X),Andhra Pradesh

Scholastic Achievements

IIT-JEE(2010): was one of the top 1% students selected nationwide (out of 4.72 lakh students)

AIEEE(2010): was one of the top 0.5% students selected nationwide (out of 11.18 lakh students)

EAMCET(2010): was one of the top 1% students qualified statewide (out of 3.83 lakh students)

Secured 23rd and 12th rank at state level(District Top) in the Unified Council Talent Test for the two

consecutive years

Technical Skills

Programming Languages: C, Verilog, Assembly, Embedded C, Matlab

Design Automation& Simulation Tools: Xilinx ISE, Synopsys, Mentor Graphics

Embedded Platforms: PIC18F µC,8086 µP,8085 µP, Arm µC,Spartan3E on FPGA

Areas of Interest

VLSI, Optical Networks, Analog Electronics

Projects

1. Full Custom Design and Semi Custom ASIC Design of Ring oscillator

Guide-Dr.K.C.Ray,IIT Patna Period: Sept’13-Nov’13

Design of ring oscillator through full and semi custom design is done using mentor graphics and

synopsys tools.

2. Unmanned Railway Gate

Guide-Dr.K C Ray,IIT Patna Period: Feb’13(2 weeks)

Designed and implemented an unmanned railway gate, using PIC 18F microcontroller, Stepper motor

and IR photo detectors.

3. Designing Portable Zoom Screen

Guide-Dr.Sumanta Gupta,IIT Patna Period: January’13-April’13

Operating computer by controlling mouse movements using objects with high intensity (l ike laser)

Computer monitor is projected on to a screen and laser movement is detected in a live streaming video

using image processing techniques.

4. Design Synthesis Framework for Networks-on-Chip

Guide- Dr. Chandan Haldar,Morphing Machines Period: May’13-July’13

Developed a flexible framework to implement Network-on-Chip (NoC) based architecture

It includes the design and implementation of an IDE based framework for realization of a NoC

subsystem with many interconnected modules like routing, flow control,arbitration and switching

modules communicating with each other through message passing or the establishment of virtual

circuits. Programming has been done in Verilog.

5. Physical layer impairment aware optical fiber network design algorithm for minimization of

CAPEX

Guide-Dr.Sumanta Gupta,IIT Patna Period:July’13-April’14

This Project aims at designing cost effective optical network by minimizing the number of components

and sub-systems placed in the network without compromising the quality of transmission

A more generic optical network with physical-layer heterogeneity, including mixed fiber types, variable

span lengths, mixed data rates, Receiver Sensitivity Dispersion compensation Modules and EDFA with

different gains is considered. Regenerators are placed to achieve desired OSNR at the receiver.

Extracurricular Activities

Elected as Technical Secretary of the Girls Hostel in Student Gymkhana Elections for the year 2012 -13

Core Committee member of Anwesha 2013, Techno-Cultural fest of IIT Patna.

Participated in dance competitions conducted at the annual fests of IIT Patna and NIFT Patna

Won first prize in Inter School level Chess Competition.

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