Project Design

DEEPAK DAVID JOSEPH PERIYANAYAGAM

Email: ************@*****.***

Ph.: +91-809*******

LinkedIn Profile: http://www.linkedin.com/in/jpdd08

PROFILE

Highly motivated and goal-oriented young Masters Graduate (in Microelectronics Systems Design) committed

to pursuing a long term career in the field of Electronics Systems Design. Demonstrating strong problem

solving skills, innovative concepts in designing automation, reliability analysis and product development with

two years of work experience as System Engineer with Infosys Limited, India (Retail Unit).

EDUCATION

2012 - 2013 MS in Microelectronics Systems Design [University of Southampton, UK]

Distinction - 71%

Modules Included: Integrated Circuit Design, Low Power Design, MOS Theory, Pass transistors, Digital

System Design, MIPS processor Design and Architecture, Embedded System Design, Synthesis for Low

Power Consumption, Nanoelectronic devices, Individual Research Project - Multithreaded Processors,

Research Methods, MSc Project - Reliability analysis of an error Robust OpenRISC processor and VLSI

Design Project - Designed a novel 32-bit Microprocessor using 0.35µm CMOS technology.

2006-2010 B.E in Electronics and Communication Engineering [Karunya University, India]

First Class with Distinction – 8.55/10

2005 - 2006 Higher Secondary [Holy Cross Matric. Hr. Sec. School, India]

Secured – 87%

PROJECTS

2013 Designed and implemented a 32-bit novel microprocessor [University of Southampton, UK]

The aim of the project was to design a novel microprocessor unit in full custom 0.35um CMOS, using

Magic for layout and System Verilog for simulation. In addition, L -Edit was used for automated place and

route while Cadence was used for design sign-off procedures. The processor is designed using the

standard cell library created by our team.

Team Size: 4 Tools Used: Magic, L-Edit, Cadence, Calibre, RTL design compiler, NCSim

Phases of development - architecture, datapath designing based on bitslice, place and route, DRC error

check, pad ring and floor planning.

Responsibilities:

Instruction Set Architecture and datapath architecture was developed based on the requirement.

Behavioural model of the Control unit and datapath was designed using System Verilog.

Integration of the behavioural model and verification of functionality was completed.

Integration of behavioural control unit and datapath created from standard library cells (following

bitslice design). Functional verification of the cross integrated processor was performed.

Assembly language programs, like multiplication, random number generator and factorial, were

written and tested on the processor. An assembler was also designed using Perl.

Place and route of control unit and datapath was performed. 2 -layer metal routing was used.

Designed and synthesised an affine transformation processor on Altera Cyclone IV FPGA,

using VHDL. [University of Southampton, UK]

Team Size: 1 Tools Used: ModelSIM, Altera Quartus II

Responsibilities:

PicoMIPS processor architecture was modified to design the above processor.

Quartus II was used to synthesise the design and JTAG was used to program the FPGA.

Individual Research Project on Multithreaded processors [University of Southampton, UK]

Concepts of ILP, TLP, Pipelining, Super pipelining, Superscalar, Multithreading and Simultaneous

multithreading were researched and a report was submitted based on the research.

A seminar was taken based on the research and a poster was designed and submitted.

Updated July 2014

Reliability analysis of an error robust OpenRISC processor [University of Southampton, UK]

The aim of the project is to build an automated system that injects soft errors into a processor at the gate

level to analyse the reliability of the given processor. The processor’s ideal behaviour is compared with

the behaviour after injecting the faults to deduce the severity of the injected fault. The above method is

used for comparing the robustness of an OpenRISC processor with and without fault tolerant techniques.

The fault tolerant technique which is used here for the analysis is known as SETTOFF.

Team Size: 1 Tools Used: ModelSIM, GNU tool chain, MakeFile

Responsibilities:

Various Faults and Fault tolerant models were studied.

OpenRISC processor core was modified to accommodate fault tolerant model.

Pi value calculation program was written in C language to test the processor.

Mutants were designed, using VHDL, to replace the components in the processor.

VHDL Testbench was designed to inject faults into the system and check for reliability.

A ModelSIM library was used to monitor the injection of faults.

2012 Designed Standard cells for a cell library [University of Southampton, UK]

The aim of the project is to design ASIC and basic cells in 0.35μm CMOS technology.

Team Size: 4 Tools Used: MAGIC, HSpice

Responsibilities:

Designed standard cells like R-dtype flip flop, Inverter, Scandtype and ScanReg.

Spice tools were used to analyse time constants, propagation delay and area of individual cells and a

data book was written based on it.

Designed a Sequence detector and Ring Oscillator [University of Southampton, UK]

Team Size: 2 Tools Used: LTSpice

Responsibilities:

Designed and implemented a sequence detector using LTSpice and prepared a report on the same.

Assisted team mate in preparing report for the ring oscillator designed.

Developed a replication monitoring system (patented) [Infosys Limited, India]

The aim of the project was to develop a tool which would reduce the time spent on monitoring the

replication activity between various servers. The tool has to read the log files from all the servers and

should provide a live progress bar for each server, which would indicate percentage of completion. If an

error is encountered then the user should be informed about the severity, type and time of occurrence.

Team Size: 1 Tools Used: Eclipse

Duration: 4 months Languages & Technologies: Java, Shell, Perl, HTML5 and CSS3.

Responsibilities:

Designed, developed and tested the tool in local and client network.

The system decreased the monitoring time from 10 minutes to 30 seconds.

2011 Developed an automation tool for asset management (patented) [Infosys Limited, India]

The aim of the project is to develop a s tand-alone application to upload data into a Digital Asset

Management (DAM) system. The application makes use of the services provided by DAM to

automatically upload data into it. The tool has to read data from excel/database and has to upload assets

based on the data. The tool increased the productivity rate by 6 times.

Team Size: 1 Tools Used: Microsoft Visual Studio, Virage MediaBin

Duration: 2 months Languages & Technologies: C#, ASP.Net

Responsibilities:

Developed and tested the tool in local and client network.

Prepared design documentation and user manual for a client’s website. [Infosys Limited, India]

2010 Developed CAN based communication interface in Electro Static Precipitator controllers

using AT90CAN128, an 8-bit microcontroller. [Bharath Heavy Electricals Limited, India]

Updated July 2014

EXPERIENCE

2013 RGIS, United Kingdom, Inventory Specialist – Part time; Annual stock auditing at stores in UK.

2010-2012 Infosys Limited, India, Systems Engineer – Full time

Design, development, impact analysis, creating design specifications, conducting reviews, reviewing

artifacts and testing of various websites or applications and working on 'Go-Live' activities.

Developed programming & scripting skills and server & database administration skills.

SKILLS

Verilog, System Verilog, VHDL, SystemC (including testbench)

HDL

Magic, L-Edit, Cadence, Calibre, RTL design compiler, Altera, Quartus II, ModelSim, NCSim, MakeFile

EDA tools

Spice tools: Hspice, Pspice, LT Spice

Hands on Cell layout design - gates, flip flops, complex digital circuits

experience RTL to verified netlist, block and chip level Floor planning, power analysis, Place & Route, Deep sub -micron

technology of 35nm, Synthesis, FPGA programming, PLC (Omron), SCADA (Siemens)

Scan-in, Scan-Out, Boundary Scan, Built-In Self-Test

Testing

C, C++, C#, Java, Perl, TCL, MakeFile, Shell Scripting (automation scripts), JavaScript, CSS, HTML

IT skills

& tools Database: MySQL, MS-SQL, db2, Oracle; Microsoft Office: Word, Visio, PowerPoint, End Note, Excel

Revision control: VSS & Subversion. IDE: Eclipse, NetBeans, Microsoft visual studio

DEVELOPMENT AND TRAINING COURSES

IELTS - Obtained overall band Score of 7.0. [India]

2012

PLC & SCADA - Attended a training course. [MSME, India]

2009

VLSI - Attended a training course. [Karunya University, India]

2009

eTRIX - Participated in Autonomous Robotics Workshop. [The Robotics Institute- IIT, India]

2008

ACHIEVEMENTS AND POSITIONS OF RESPONSIBILITY

Student Helper on open day - Assisted prospective students and helped them to complete registration

2013

formalities. Developed communication and organi sing skills. [University of Southampton, UK]

Volunteer at Graduate Ceremony - Greeted graduates on their way into their ceremonies, offered

general advice and help to graduates and parents on the day of ceremony. [University of Southampton, UK]

2011-2012 Organizing Secretary - Effectively planned and organized project parties within the Retail Unit. [Infosys

Limited, India]

2008-2010 Online strategy games – Won titles playing DotA and Counter Strike in intra-college tournaments. [India]

2009 Movie Spoof – Spoofed two movies with a team of 10 members within a time span of 10 min utes and won

first prize. [PSG, India]

2008 Robot Sumo Wrestling – Designed and built a robot which is capable of simultaneously fighting other

robots inside a ring and won third prize. [SRM University, India]

2005-2006 School Pupil Leader - Lead the school of 6000 pupils and received award of excellence for my leadership

skill from my institution Chairman. [Holy Cross Matric. Hr. Sec. School, India]

PERSONAL DETAILS

D.O.B. 08- NOV-1988

Address 31, Anubavarunodya Apartments, Swamipillai Street, Choolai, Chennai – 600112

Hobbies Swimming, online gaming, Volleyball, acting

Languages English, Tamil

Marital Single

Status

Passport Yes

REFERENCES

Mr Iain McNally, Professor, University of Southampton E-mail: *.*******@***.*****.**.**

Dr Basel Halak, Professor, University of Southampton E-mail: ***@***.*****.**.**

Updated July 2014

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