Engineer Design

ALEKSANDR KUPCHIK

Cell: 603-***-****

***********@*******.***

SUMMARY

Hardware design engineer with over 15 years of experience in high-speed

analog and digital design in the voice, data networking and measurement

industries.

. Project leader with a proven record of accomplishment for delivering

cost-effective, reliable designs on time. Outstanding analytical,

problem solving and troubleshooting capabilities.

. Experience with all aspects of embedded hardware product development,

including circuit design, FPGA design and simulation, mechanical

design, thermal analysis, prototype and production bring-up and

debugging and compliance testing including EMI and safety

certifications.

. FPGA design and verification. Experience with VHDL/Verilog - synthesis

and simulation. Experience with XILINX FPGA technology and tools.

. TCL scripting.

. Solid understanding of low power analog design techniques, analog

layout for performance with knowledge of analog system definition,

system architecture, simulation, and circuit design.

. Experience with high speed serial connections (SerDes links) for inter-

chip communication and distributed parallel processing technology,

including PCIe Gen 2 and 10 Gb/s Ethernet.

. Diverse specialties include Digital Signal Processors (DSP) from TI,

PowerPC line from Freescale, system architecture, DDR2/ DDR3 memory,

power design and board /system-level design

. Strong theoretical background and comprehensive understanding of voice

and data telecommunication specifications and implementation.

. Experience designing complex high speed PCB with HyperLynx high-speed

signal simulation tool.

. Hands-on debugging experience using high-speed oscilloscopes and

application-specific analyzers.

PROFESSIONAL EXPERIENCE

A2E Technologies, Burlington, MA

2012-

Present

Principal Hardware Engineer

. Technical Lead, responsible for development, design, schematic entry,

FPGA design, debugging and bring up complex hardware embedded systems.

. Designed and developed a board that combines analog and digital

subsystems intended for ATE application. Design included analog

instrumentation circuitry, ADC, low noise power design and complex

FPGA.

. FPGA coding and simulation using a Xilinx Spartan 6 FPGA. Design

includes PCIe interface, DDR2/ DDR3 memory subsystem and high speed

signaling.

. FPGA coding and simulation using a Xilinx Spartan 3AN FPGA.

Implemented Multi Boot application.

. Coordinated post-design, HyperLynx, simulation effort to

validate high-speed design

. Bring up, debugging and DVT.

Dialogic Research, Needham, MA

2008- 2012

Principal Hardware Engineer

. Solely responsible for architectural design, VHDL coding, and

simulation of PSTN Time Slot Interchanger using a Xilinx Spartan 6

and Virtex 4 FPGA and external VCXO PLL.

. Designed and developed a DSP subsystem based on TI TCI64xx DSP

family. DSP farm was developed as part of Telecom Carrier Media

Gateway to provide high-density video solutions.

. Worked closely with software team to resolve software and hardware

issues of CPU and peripherals

. Designed high performance data plane switch fabric utilizing

multilayer Ethernet switch from Marvell. Design included SerDes

based interconnects with port speeds up 10 Gb/s.

. Led successful architectural design of highly integrated SS7 PCI

Express board. Designed components included an integrated Power QUICC

III PC from Freescale, DDR2 SODIMM, PCI Express interface and PSTN

and IP network interfaces.

. All projects included hardware bring-up, DVT and release to

production.

NMS Communications INC., Framingham, MA

2005- 2008

Principal Hardware Engineer

. Led successful architectural design of the ATCA board, designed for

media and video processing.

. Individually contributed to analysis and design of the high speed

Gigabit Ethernet fabric solution that allowed on-board and inter-

board packet-based communication. It was based on the multilayer,

multi port Gigabit Ethernet Switch from Broadcom. Participated in

design to support VLAN based solution.

. Coordinated post-design simulation effort to validate high-speed

design.

. Designed and architected the CG6565 PCI-X board which included a

PowerPC, a pool of DSP-based media processors and PSTN and IP network

interfaces. The architecture was developed for VOIP solutions

including media gateways, media servers, comprehensive IVR systems

and other applications.

STARENT NETWORKS, INC., Tewksbury, MA

2001-2005

Principal Hardware Engineer

. As member of the initial hardware team, designed, developed, and

successfully deployed the ST16 Intelligent Mobile Gateway.

. Led successful architectural design and development of highly

advanced system control card based on a multi-core MIPS CPU and

incorporating switching facilities for data management and traffic

control. Designed components included DDR SDRAM, PCI, on-board

Gigabit Ethernet network, Network Processor and several FPGAs.

Devised an algorithm to support redundant applications and developed

a reliable protocol to interface two system cards for fail-safe

environments.

. Analyzed system design and timing characteristics of DDR SDRAM sub-

section to ensure that design and configuration settings were

appropriate for future expansion. Hands-on experience in debugging

DDR and DDR2 SDRAM with high-speed oscilloscope and application-

specific analyzer.

. Designed and implemented high-speed, fully redundant internal control

network employing packet switching and SerDes technology. High-speed

network and protocol analyzers were used to perform debugging.

. Worked closely with software team to resolve software and hardware

issues of CPU and peripherals.

. Participated in defining the voice and VOIP solution for the mobile

gateway. Led architectural design and development of the multi-port

DS3 line card, as part of the VOIP system. Designed low-jitter clock

distribution network to support product requirements. Card employed

FPGA, SerDes and various DS3 circuitries.

CASTLE NETWORKS, INC. (Unisphere Networks, Currently Siemens Networks),

Westford, MA 1998-2001

Principal Project Leader

. Participated in architectural development of a new generation of high-

performance, high-density, carrier-grade digital telephone switches.

These systems remain in use today by multiple customers.

. Led the architectural design and development of a high-density TDM

switching card. The design employed a complex DS3/DS1 termination

controller, Motorola Power-PC CPU, Altera FPGAs and high density TDM

switch.

. Led research and final implementation of redundancy solution to cover

both front-end DS3/SONET line and backend functional cards.

. Participated in design and development of SS7 subsystem for high-

availability implementation.

LANCAST, INC. (Currently Metrobility Networks).Nashua, NH

1995-1998

Principal Project Leader and Chief Scientist (1997-1998)

. Performed numerous pure research tasks to gauge the feasibility of

new technology approaches.

. Participated in architectural development of a new generation of high

performance, multimedia-ready Layer 2 and Layer 3 Fast Ethernet

switches.

. Led the architectural design and development of an SNMP-managed

Ethernet switch. The design employed an embedded RISK CPU with a

switching fabric based on PCI bus interconnects. Participated in

software debugging and developed an optimized PCI arbiter.

Design Engineer (1995-1996)

. Defined and developed innovative high-speed design approach for a low-

latency, cost effective Fast Ethernet media translator. Cisco and

Cabletron selected it as their "Product of Choice"

PATENTS

Two Patents developed on several Lancast designs.

EDUCATION

BS, Electrical Engineering, STATE POWER UNIVERSITY, Ivanovo, Russia

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