Project Engineering

N. PARTHASARATHY

No: *,*nd cross, eMailID:***********@*****.***

Krishna nagar, Phone no:+918*********

Lawspet, Pondicherry -605003.

CARRIER OBJECTIVE

To have a progressive and challenging career while being resourceful, flexible and

innovative, also to work for the betterment of the organization with full commitments .

EDUCATIONAL QUALIFICATION

Course Institution Name Year of Passing CGPA/Percentage

B.Tech

(Electronics and Manakula vinayagar

2014 7.67

Communication Institute of technology

Engineering)

Petit Seminaire

H.S.C Higher Secondary 2010 73.3%

school

Petit Seminaire

Matriculation Higher Secondary 2008 77.2%

school.

TECHNICAL SKILLS

Programming Languages: VHDL, Verilog and C.

Professional packages : Altera.

AREA OF INTEREST

• VLSI.

• Digital Electronics.

PUBLICATIONS AND CONFERENCE

• INTERNATIONAL ORGANISATION FOR SCIENTIFIC RESEACH (IOSR)

• AMERICAN JOURNAL OF ENGINEERING RESEARCH(AJER)

• NATIONAL LEVEL CONFERENCE in Bannari Amman Institute of technology

ACADAMIC PROJECT

Title: DESIGN OF HIGH SPEED, LOW POWER, AREA EFFICIENT SQUARE ROOT

CARRY SELECT ADDER

Description: It is said that in VLSI the three main areas to be concentrated are area, power and

speed. Literature review shows that satisfying any of the two main factors, we can get the

efficient output from the other factor. The designed adder (SQRT CSLA) gives efficient output

in all the three areas. This work uses a simple and efficient gate-level modification to

significantly reduce the area and power of the CSLA.

Based on this modification 8-bit, 16-bit, 32-bit, and 64-bit square-root CSLA (SQRT

CSLA) architecture have been developed.

The proposed design has reduced area as compared with the regular SQRT CSLA with

only a slight increase in the delay.

The result shows that the proposed CSLA structure is better than the regular SQRT

CSLA with an efficient Binary to Excess 1 Converter (BEC) logic.

The main idea of this work is to use BEC instead of the RCA with Cin=1in order to

reduce the area and power consumption of the regular CSLA.

MINI PROJECT

• Project in wire breakage detector.

• Missile jamming using global system for mobile communication

• Designed a quad copter ( A SURVEILLANCE ROBOT ) that can be controlled by

android, GSM and remote ( using transreceiver )

CO-CURRICULAR ACTIVITIES

• Attended one day workshop on Network security held in Anna University.

• Attended one day workshop on Introduction to Android, Cloud Computing, and Ethical

hacking.

• Attended workshop on Android held in SSN college of Engineering.

INDUSTRIAL EXPOSURE

• Visit Spinco chip production company ( Bangalore )

• Training at HCL info system, Sedarapet( Puducherry )

• Visit to STC info solution ( Testing and Automation )

PERSONAL TRAITS

• Leadership.

• Adaptable

• Respect to individual

• Creative thinking

PERSONAL DETAILS

Father’s Name : Mr.D. Nandagopal

Mother’s Name : Mrs.N. kavitha

23th July 1993

Date of birth :

English, Tamil.

Languages known :

Interests : History

PLACE: Puducherry.

(N.PARTHASARATHY)

DATE :

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