S hivani Garg
H.No. ****, N.H.B.C, Sector-**,
Panipat-132 103 (Haryana) India
E-mail : *******.****.****@*****.***
Contact : +91-852*******, +91-941**-*****
OBJECTIVE
Looking forward to be a part of the research and development team where I can learn
and grow my technical and professional skills.
CURRENT OBJECTIVE
To be a part of research and project team as an intern for Six Months (Dec’14/ Jan’15 -
M ay’15/ Jun’15) duration in RTL Design and Verification using SystemVerilog and UVM
i n VLSI Design .
EDUCATIONAL QUALIFICATION
Qualification Institution Year Board /University Percentage/
G rades of Marks
M.Tech IT M University, Pursuing ITM University, 9.81/10
(VLSI Design) Gurgaon Gurgaon (Haryana) (upto 2nd
( Haryana) India I ndia Semester)
B.Tech University Maharishi Dayanand 81.6% (1st r ank in
(E&CE) I nstitute of U niversity, Rohtak Department)
E ngineering & 2013 ( Haryana) India
Technology,
Rohtak
( Haryana) India
Senior DAV Centenary Central Board Of 90.8%
Secondary Public School, 2009 Secondary Education
Panipat (CBSE), New Delhi,
( Haryana) India I ndia
Secondary DAV Centenary Central Board of 91.4%
Public School, 2007 Secondary Education
Panipat (CBSE), New Delhi,
( Haryana) India I ndia
TECHNICAL SKILLS
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Software Languages C, C++, M IPS, Embedded C
Operating Systems Windows, Linux
Packages MS Office, Excel, Power Point
VHDL, Verilog HDL, SystemVerilog
Scripting Languages Shell Scripting, Perl/tk, Tcl/tk
EDA & Simulation Questa Sim10.0b, Xilinx ISE & System Ed., Cadence - NCSim,
softwares RTL compiler, SoC Encounter, Viruoso, Gcc compiler, icarus
verilog, Synopsys- TCAD, Custom designer, MAT LAB, CppSim, LT
Spice, Tanner, Keil µvision3
Hardware Platform Xilinx FPGA Spartan 3AN, Digilent Nexys3 Spartan6,
M icrocontoller 8051 Development board
Other Softwares Management Scientist, Pert Chart Expert
Interest Areas Digital System Design, FPGA Implementation, Verification Using
SystemVerilog, UVM based Verification
SCHOLASTIC ACHIEVEMENTS
1. Recognized as a student of Dean’s list during M.Tech in 1 st and 2nd Semester.
2. Qualified GATE 2013 with 98.3 percentile and a GATE Scholar as a Teaching
Assistant during M.Tech.
3. 1st Rank holder in B.Tech with 81.6%.
4. Won Merit Scholarship in all 3 years of B.Tech and 2years of M.Tech from CBSE.
COURSES
Design & Analysis of Computer Architecture,
D igital VLSI Design,
Data Structures and Algorithm,
Semiconductor Device Modelling & Technology,
D igital System Design with VerilogHDL,
Computer Aided VLSI Design,
E mbedded System Design,
V LSI Fabrication and Technology,
Low Power VLSI,
SystemVerilog for Verification
PUBLICATIONS
A Survey on FPGA Prototyping for Feature Extraction of I mages Using
D ifferent Edge Detection Techniques …communicated
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I n this paper, a broad survey of hardware implementation of different image edge
detection techniques for different kind of images and videos comparing their hardware
u tilization, architectural features and design parameters such as area, time, power is
p resented.
Coverage D r iven Assertion based Efficient Verification
E nvironment for P rogrammable I n te rval T imer Core ...to be
communicated
In this paper, a coverage driven verification environment has been created for
p rogrammable interval timer which uses VMM methodology for verification. The overall
f unctional and assertion coverage achieved is 97%. If code coverage is included then
overall coverage reported is 80%.
PROJECTS
Design and Verification of 40G Ethernet using SystemVerilog*
Summary:
The Verification environment includes object-oriented programming, constrained-
random stimulus, advanced data types and functional coverage provides an effective &
efficient way to verify the Ethernet core and recover clock from data.
Functional Verification of P rogrammable I nterval Timer Core using
SystemVerilog
Summary:
I t includes creation of a constraint-random verification environment for
p rogrammable interval timer using a t ransaction-based approach. I t is a
h ierarchal environment which is very easy to be built and debugged. T he overall
f unctional and assertion coverage achieved is 97%. If code coverage is included
t hen overall coverage reported is 80%.
RTL to GDSI I conversion of I mage Enhancement operations: Contrast,
b rightness, threshold, Inversion using Cadence SoC Encounter
Summary:
GDSII is extracted for the DUTs for image enhancement operations like
Contrast Operation, Brightness manipulation, Inversion, Threshold operation.
GDSII is GDS I I is a database file format which is the de facto industry standard
for data exchange of integrated circuit or IC layout artwork.
RTL to GDSI I Conversion of a Booth multiplier using Cadence SoC
E ncounter
Summary:
4-bit Booth Multiplier is synthesized using RTL compiler . Then GDS I I is extracted
f rom the netlist obtained using RTL compiler.
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RTL to GDSI I Conversion of a 4-bit ALU using Cadence SoC Encounter
GDSII has been extracted for a 4-bit ALU (Arithmetic Logic unit) design . Addition,
subtraction, Increment, Decrement using multiplexer are done.
FPGA Implementation of Real-Time System for Medical I mage
P rocessing using VerilogHDL *
Summa ry:
Implementation of Image enhancement techniques in the spatial domain
l ike contrast manipulation, brightness manipulation, inverting images,
t hreshold operation are done on Spartan 3AN.
Hardware and Software: FPGA, Xilinx ISE, MATLAB and VerilogHDL
FPGA prototyping of Synchronous F I FO using VerilogHDL*
A synchronous FIFO is a First-In-First-Out queue consisting of a storage array with
control logic that manages the read and wri te of data and generates status f lags.
A Synchronous FIFO has a single clock port for both data-read and data-wri te
operations Synchronous FIFO of 8x8 has been implemented on Spartan6 using
VerilogHDL
FPGA prototyping of 4-bit Booth Multiplier using VerilogHDL
Summary:
A 4-radix booth multiplier is the extended booth multiplier which has been
i mplemented on FPGA using Verilog HDL in Xilinx. This architecture is
used for reducing the number of partial products by a factor of 2 to achieve
faster multiplications of signed numbers.
FPGA prototyping of Finite State Machines (Traffic light controller,
Vending Machine, Sequence detector) using Verilog H D L
Summary:
FSM like Traffic light controller, Vending Machine, Sequence detector is designed
and synthesised using Verilog HDL in Xilinx.
FPGA prototyping of Keyboard and Seven segment I nterfacing using
VerilogHDL
Summary:
Data entered from PS2 Keyboard is displayed on seven segment using
VerilogHDL. I t has been implemented on FPGA Spartan6 using USB port
Design of CMOS by Tw in-Tub process using Synopsys TCAD
Summary:
Using TCAD a process sequence to fabricate the twin-tub CMOS structure is
designed. Sentarurus structure editor, process, structure device, structure
workbench, structure mesh, Svisual are used.
Security system using 8051
Summary:
T his is a simulation of security system for providing secured entry through door.
E nt ry is password secured. In this a user can only pass through the entry if user
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p rovides a security password. If user enters a wrong password continuously for 3
t imes a buzzer will get activated to alert security.
Hardware Used: M icrocontroller 8051 Development board, LCD display, Keypad,
S tepper motor, Buzzer.
Automatic Room Light Controller using 8051
Summary:
T his project is for automated control of room light with a view of resource
management. As soon as someone enters a room though designated door room
l ights will be switched. I t will keep count of number of visitors entered into room
and exiting room. When number or visitors entered room matches visitors exited
f rom i t, room lights will be switched off automatically.
Hardware Used: M icrocontoller 8051 Development board, IR sensors, Relay
* currently working on these
TRAINING & INTERNSHIP
Six weeks t raining in “Verification using SystemVerilog” at Xinoe Systems Pvt.
L td in June-July 2014.
Six weeks internship at KC Robotics and Embedded Pvt L td. Noida in June - July
2011
Six weeks internship at Panipat Thermal Power Station, ( A Unit of Haryana
Power Generation Corporation L td.), Panipat in June - July 2012
Six months internship at Advance technology, Chandigarh from Jan -June 2013
GUEST LECTURES/ SESSIONS DELIVERED
18th – 20th A ug, 2014: CAD for VLSI and In tegrated Circuit Technology at
M aharani Girls College of Engineering, Jaipur
WORKSHOPS & TRAININGS ATTENDED
28th -30th M ay, 2014: Training in Custom Designer (synopsys tool) as a participant
of Analog Design competition by Synopsys at CDAC, Noida,.
24th -28th M ar., 2014: Special Skills Development Program in Project Management
for M.Tech VLSI Design at ITM University, Gurgaon
08th M ar., 2014: “SoC Encounter – Design Flow” by Cadence Design System at
I TM University, Gurgaon.
10th Feb., 2014: One day seminar on Int roduction to VLSI Design by ST
M icroelectronics, Noida.
25th Jan., 2014: “Olympus – Placement & Route” by Team MentorGraphics, Noida
a t IT M University, Gurgaon for MTech VLSI Design students.
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14th Nov., 2013: “Workshop on FPFA” for Faculty and Students of ITM University,
Gurgaon.
05th Oct., 2013: Physical Design: An Indust ry Level Design Approach for MTech
V LSI Design and BTech VLSI Group at ITM University, Gurgaon.
30th Sept., - 07th Oct., 2013 : Special Skills Development Program in linux and
Shell Scripting by Fostering Linux.
ABOUT MYSELF
Keen learner with ability to learn & imbibe new knowledge with ease.
Honest, Hard Working.
Commit ted to the tasks undertaken, Learning and Working Approach.
Team Player Spiri t
EXTRA CO-CURRICULAR ACTIVITIES
Co-ordinator of National Conference on Electronics & Communication
Technologies 2014 (NCECT-2014), IT M University Gurgaon.
Organizer of workshop on Robotics in college
Volunteer in Science conclave in college premises.
Won maths and science quiz in school premises.
REFERENCE
1. Dr. Neeraj Kr. Shukla
Associate Professor-Department of EECE
Project Manager-VLSI Design
ITM University, HUDA Sector-23A,
Gurgaon-122017 (Haryana) India
E-mail: *************@********.***
Contact: +91-921*******
2. Prof. Swaran Ahuja
HOD- Department of EECE
ITM University, HUDA Sector-23A,
Gurgaon-122017 (Haryana) India
E-mail: ***********@********.***
Contact: +91-997*******
3. Ms. Rakhi Nangia
VLSI Design Lead
Xinoe Systems Pvt. L td.,
P lot No. 38, Electronics City, Sector 18
Gurgaon-122 015 (Haryana) India.
E-mail: m ******@*****.***
Contact: +91-991*******
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PERSONAL DETAILS
Father’s Name M r. Naresh Garg
Date of Bir th September 13,1992
Sex Female
Mari tal Status Single
Nationality I ndian
Languages Known E nglish, H indi
DECLARATION
I declare that the information given above is t rue and correct to the best of my
k nowledge.
Place: Gurgaon (Haryana)
Date: S H IVAN I GARG
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