M.Tech in Microelectronics and VLSI design, IIT Roorkee.

Ashish Shrivastava

M.Tech (Microelectronics and VLSI), IIT ROORKEE

Email: ******.***********.*****@*****.***

Phone: 962-***-****

Current location- Bangalore, India.

Areas of interest: Digital design, Analog design, ASIC, Memory design, Reliability

issues in modern CMOS devices.

Educational Year Board/Institution CGPA/%

qualifications

M.Tech 2014 IIT ROORKEE 7.95

(Microelectronics and

VLSI)

B.E (Electronics and 2011 Rajiv Gandhi 76.7

Communications) Technical University,

Bhopal

St. Xavier’s High

Twelfth (I.S.C) 2007 69

school, Jabalpur

St. Xavier’s High

Tenth (I.C.S.E) 2005 75

school, Jabalpur

PROJECTS

M.Tech dissertation- IIT ROORKEE

Modeling of Negative Bias Temperature Instability Effects in Silicon Nanowire

Transistors (June 2013 to June 2014).

First reliability tests were performed on the devices at different voltages and temperatures.

Then a model was generated based on seperate degradations due to interface and oxide trap

charges using MATLAB. The simulated results were compared with experimental results,

and it was found that the model agrees well with experimental results.

Implementation of period finder on Xilinx using SPARTAN kits (Course project).

A period finder was designed to calculate the time period of any incoming signal.

In idle mode, the system waits for the START command. In normal mode, the module waits

for the rising edge of the input, and upon detecting a rising edge the module enters the period

state. In period state, the module counter is incremented by 1 until second rising edge is

detected, upon which the module sends a DONE signal to show the operation is complete.

The programming was done in a VHDL module in Xilinx, and the code was implemented on

a SPARTAN kit.

Two stage Miller OPAMP by gm/ID methodology (6 months)

A two staged Miller operational amplifier was designed as part of curriculum project. The

final measurements that were obtained are gain=70 dB, phase margin=58 degrees, slew

rate=10V/μs (@ CL= 1pF), gain bandwidth=182MHz and power dissipation less than 1mW.

The project was designed with TSPICE.

SKILLS AND ACHIEVEMENTS

Computer skills C, Verilog HDL, VHDL, UNIX, Perl.

Software Packages Xilinx, LabVIEW, TSPICE, MATLAB

Academic Qualified GATE 2012 with AIR 213 (GATE score 801) and

Achievements 99.91%ile

Extra curriculars Placement representative for post graduates at IIT Roorkee from July

2013 to June 2014.

st

Won 1 prize in inter district philately competition (Oct 2008)

Active participant in event anchoring/management during

school and college.

Was part of the annual tech fest organizing commitee during

graduation.

Active participant in events organised by Himalayan Explorers’Club,

IIT Roorkee.

Courses Taken at IIT Digital VLSI design, Analog VLSI design, Data

structures, Computer system architecture, Semiconductor device

modeling, VLSI fabrication technology

Academic experience Worked in fabrication lab at IIT Roorkee, as a part of

dissertation. Experience in handling fabrication lab equipment

and characterisation equipment (eg KEITHLEY 4200 SCS)

and 2636 SMU.

Worked as teaching assistant at IIT Roorkee and supervised

undergraduate tutorial classes for Digital Electronics and

served as grader for the same. Also supervised post

graduates in solid state devices laboratory.

Languages English (S/R/W), Hindi (S/R/W), German (S/R)

PERSONAL DETAILS

Father's Name: Mr Anil Kumar Shrivastava

Date of Birth: June 13, 1989

Gender: Male

Contact No: 096********

Category : General

REFERENCES

Dr. Sanjeev Manhas Dr. Anand Bulusu

Assistant Professor IIT

Assistant Professor IIT

ROORKEE

ROORKEE

********@****.*****.**

********@****.*****.**

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