Pursuing M.Tech in VLSI& Computer Engineering from IIIT-Hyderabad

ANKIT TUTEJA

S/o Vijay Kumar Tuteja

H.No. *** Sector-4 Urban Estate,

Gurgaon 122001 Haryana

Ph.No. : +91-965*******

Email:*****.********@*****.**.**

SUMMARY

To secure a challenging position where I can effectively contribute my skills and ensure my growth through the

organization’s growth, possessing competent Technical Skills.

TECHNICAL SKILLS

General Purpose Languages: C, Embedded C, C++, Data Structure and HTML.

Domain Specific Languages: Basics of Verilog, System Verilog, H-spice.

Scripting Languages: Shell Scripting, Python, JavaScript.

Tools: Cadence’s Virtuoso Tool, LTspice, Modelsim.

Protocols: (Designed and Verified in System Verilog using Questasim tool) I2C, APB, SPI, UART, UART verified fully

functional on FPGA (Xilinx Vertex5 XUPV5-LX110T).

Domain Knowledge:

Analog and mixed signal design: Operational Amplifiers.

Computer Architecture: Pipelining, hazard detection and forwarding in MIPS processor.

VLSI Architecture and Design: Designing digital hardware using mux, comparators, adders and gates.

PROJECTS

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1. 6T SRAM in retention mode along with bit-cell study:

Description: This thesis explores the design and analysis of Static Random Access Memories (SRAMs), focusing on

optimizing delay and power. The SRAM access path is split into two portions: from address input to word line rise

(the row decoder) and from word line rise to data output (the read/write data path). Techniques to optimize both

of these paths are investigated. I determined the optimal decoder structure for fast low power SRAMs. I investigated

tracking circuits to limit bit-line and I/O line swings and aid in the generation of the sense clock to enable clocked

sense amplifiers.

2. 32 bit pipelined MIPS processor:

Description: Designed and verified 32 bit pipelined MIPS processor along with hazard detection and data forwarding

in Verilog.

3. 16x16 BCD Digit Multiplier:

Description: Building blocks were 1 digit BCD Multiplier, BCD Adder and carry save adder. Designed In Cadence’s

virtuoso at 180nm technology .

4. Designing a Telescopic and a Two-Stage Operational Amplifier:

Description: A telescopic and a two-stage operational amplifier in cadence’s virtuoso tool at 180nm technology at 1V

voltage supply and total current of 150uA with following specifications. Gain of 73dB and CMRR of 77dB with

Capacitive Load of 1pF.

5. Online Students Portal on Web2py:

Description: A portal (a website) using WEB2PY that had access to both students and faculty members where

students can view their grades and attendance and faculty can view profile of any student and upload marks and

attendance of the students for his particular subject. Also Implemented hash tags and threads section where studen ts

as well as faculty can post.

6. Access Control System:

Description: Access control was based on RFID and Password locking using Atmel AT89C51. In order to open a lock

one needs to swipe the card and if the card is valid, the system asks for the password. Programming for the same was

done in Embedded C and chip was burned using Keil Software. Modified this project to work on Xilinx Vertex5

XUPV5-LX110T FPGA along with GSM interface.

7. C & Data Structure Project:

Description: C project on banking consisting of all the basic functions such as withdrawal, savings, credit and transfer.

Also made a Library Management System using data structures that consisted of database of students and books (as

a linked list), books issued by student.

EDUCATION

Session Degree/Qualification University/School CGPA/Percentage

7.94(2nd Semester)

2013-2015 M.Tech (VLSI & CE) International Institute Of Information

Technology Hyderabad

2009-2013 B.Tech (ECE) Jaypee Institute Of Information 8.1

Technology, Noida

2008-2009 AISSCE (CBSE) Blue Bells Model Sr. Sec. School 86.66%

2006-2007 AISSE (CBSE) Blue Bells Model Sr. Sec. School 90%

STRENGTHS

Knowledge Sharing, Team Player, Cooperative Skills, Time Efficient, Self-Determined.

Personal maturity, Optimism, Emotional Intelligence.

Self Confidence, Hard Working.

C0-CURRICULAR ACTIVITIES

Presently the Student’s Placement Coordinator and Class Representative.

Selected in Ericsson Empower University Program and successfully completed.

Leading role in volunteer management in INDIAN GRAND PRIX-Formula One World Championship 2011.

Worked as Cultural Coordinator at college’s youth club JYC (Jaypee Youth Club) with active participation in cultural

events.

Leading dancer in college dance group Mystic Madness. Represented college dance group at IIT ROORKEE’s Cultural

Fest and won second prize at our college fest.

Awarded Certificates of Merit at school level in Math Olympiad, Bournvita Quiz Contest, National Bal-Jyoti

Examination (conducted by NIIT).

I hereby declare that information furnished above is true to the best of my knowledge.

(ANKIT TUTEJA)

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