VLSI Design

M anoj Sukhavasi

I ndian Institute of Technology Madras, Chennai

C ontact : +91 - 961-***-**** *********@*****.***

EDUCATION

Program Institution Year of completion

%/CGPA

Dual Degree* in

Indian Institute of Technology Madras, Chennai 7.69/10 2013

Electrical Engineering

XII Vijaya Ratna Junior College, Hyderabad 94.5% 2008

X Aditya Public School, Kakinada 87.8% 2006

*B.Tech in Electrical Engineering and M.Tech in Microelectronics and VLSI Design, Minor in Operations Research

S CHOLASTIC ACHIEVEME NTS

Secured All India Rank 454 in the (IIT-JEE) Joint Entrance Examination- 2008

Secured place in top 1 percentile in NEST-2008(National Entrance Screening Test)

R ELEVANT COURSE WORK

Digital IC Design Advanced Topics in VLSI

CAD for VLSI Design DSP Architectures and Embedded Systems

Digital Design Verification Computer Organization and Microprocessors

VLSI Design Lab Microprocessor Lab

S KILLS

Programming Languages: python, C, Verilog HDL, Perl

Packages: Xilinx ISE, ModelSim, Eldo, Matlab

P ROJECTS

Approximated Hardware for Pedestrian Detection (Dual Degree Project) Jul’12– Jun’13

Incorporated the notion of approximate computing in pedestrian detection at architectural and algorithmic

levels

Designed and implemented the approximated pedestrian detection system on Xilinx virtex-5 board.

2D Maze Game on Hardware Jan’12 – Apr’12

Designed a 2D Maze game in Xilinx ISE environment and implemented it on FPGA with VGA monitor as

visual interface and PS2 Keyboard as input

Efficient Logarithmic Converter Jan’12 – Apr’12

Modified and implemented an efficient logarithmic converter based on piecewise linear approximations

The design minimizes the maximum relative approximation error

FIR Filter Jan’12 – Apr’12

Designed and implemented a complete low pass FIR filter on FPGA

Interfaced with ADC and DAC modules on FPGA board for accessing analog inputs and outputs

P ROFESSIONAL EXPERIE NCE

May’11 – Jul’11

Avaya India Private Limited, Pune Technical Summer Intern

Integrated Avaya IP soft phone (Avaya Flare) with Avaya IP office

Developed various features for this soft phone like incoming, outgoing calls and managing phonebook

Studied various video codec algorithms like H.263 and analyzed how these video codecs are being

described and sent in Session Initiation Protocol (SIP)

P OSITIONS OF RESPONS IBILITY

Counsellor, Guiding and Counselling Unit Alakananda Hostel IIT Madras Aug’11 – Apr’12

Reached out to the first years to help them with the transition to their college life

Helped students with issues related to academic and social life

E XTRA - CURRICULAR ACTIVITIE S

Volunteered in Environmental Conscious Group(ECG) of National Service Scheme Aug ‘08– Apr’09

Conducted several environmental awareness competitions in government schools

Participated in several rallies conducted to increase environmental awareness

Volunteer for Students Amenities Centre in my Hostel for academic year 2008-09

Finalist for manual robotics competition in Mechanica’10

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