Design Engineer

Pretty Mariam Jacob

Flat No: ***, BMS Residency, 5th main, 7th cross H S R Layout, Bangalore, 560068

Ph No: +918*********, Email id: ************@*****.**.**,

in.linkedin.com/pub/pretty-jacob/64/966/7b2

CAREER OBJECTIVE

To get acquainted with latest technologies in VLSI field and to get an opportunity to apply my technological skills

into practice.

EDUCATION

MTech (VLSI Design) 2012-2014: Vellore Institute of Technology, Vellore, CGPA: 9.4 (College Topper)

BTech (Electronics and Communication) 2006-2010: Mar Baselios College of Engineering& Tech,

Trivandrum, India with 8.5 CGPA (College Topper and fourth in the Kerala university)

XII – 2006: St Antony’s Public School (CBSE), Kerala with 92%.

X – 2004: MGM Residential Public School (CBSE), Kerala with 95%

SKILLS

HDL HVL Simulator Synthesis Tool Backend Tool DRC/LVS Scripting Programming

Verilog Specman ModelSim RTL Compiler SoC Encounter Virtuoso TCL Embedded C

System Altera PERL Assembly

Verilog Quartus II

Basics

MATLAB

Simulink

NCLaunch

WORK EXPERIENCE

Oct ‘2013 to May ‘2014

Intel India, Bangalore

www.intel.com

Role: Internship

Efficient SoC/IP Validation Convergence

Responsibilities:Validation of Intel Desktop processors, Automation using Perl, Coverage analysis

Technologies: Perl, Specman, System Verilog, Incisive metrics center Coverage analysis, Specview

Dec ‘2010 to June ‘2012

Infosys Ltd, Mcity, Chennai

www.infosys.com

Role: Systems Engineer

Anti-Money Laundering and data warehousing - Bank of America, USA

Technologies:Actimize, UNIX, Shell Scripting, Toad (Oracle for Database)

Tata Elxsi, Trivandrum BTech Main Project

Jan ‘2010 – April ‘2010

www.tataelxsi.com

Anti-Pinching in Sun Roof – Tata Elxsi

Responsibilities:Involved in design and development of the simulation model for implementing anti-pinching in

sunroofs of automobiles.

Technologies: Matlab, Simulink

ACADEMIC PROJE CTS

July ‘2012-Nov ‘2012

Error Compensation for Fixed Width Booth Multiplier

Synthesis of Fixed Width Multiplier using Modified Booth Algorithm and error compensation circuit to

compensate the truncation error for fixed width multiplier.

Tools Used: ModelSim, RTL Compiler

Design of Booth Multiplier Using 32 – Bit CCS Adder For High - Speed Applications

Jan ‘2013-April ‘2013

Design and Synthesis of 32 Bit Conditional Carry select (CCS) adder with Successively Incremented Carry

Number Block (SICNB) for high speed applications and implementation of SICNB CCS adder in booth multiplier

Tools Used: Cadence NCLaunch, RTL Compiler, SoC Encounter

Jan ‘2013-April ‘2013

Design of second order sigma delta modulator

Modeling of second order sigma delta modulator in Verilog –A and comparative study of second order and first

order sigma delta modulator in Matlab and Cadence Spectre-S

Tools Used: Cadence Virtuoso (Verilog A), Matlab, Simulink

Implementation of 16 Bit Floating point multiplier using Residue Number System

Jun ‘2013-Aug ‘2013

Tools Used: ModelSim, RTL Compiler

**Presented at the IEEE ICGCE 2013 held on Dec 12-14, 2013 at RMD Engineering College, Kaveripettai

(http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6823427&queryText%3DImplementation+of+16

-Bit+Floating+Point+Multiplier+Using+Residue+Number+System)

**Selected for Journal INTERNATIONAL JOURNAL OF TRUST MANAGMENT IN COMPUTING AND

COMMUNICATIONS

Jun ‘2013-Aug ‘2013

Implementation of Floating point MAC using Residue Number System

**Presented at IEEE ICROIT-2014 Conference held on 6-8 February 2014

(http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6798385)

**Published in Journal of Theoretical and Applied Information Technology 20th April 2014. Vol62 No.2.

(http://www.jatit.org/volumes/Vol62No2/17Vol62No2.pdf)

ACHIEVEMENTS AND OTHER ACTIVITIES

Top scorer in VIT University for MTech VLSI Design consistently for first and second year and eligible for merit

scholarship in both the years.

College Topper and Best Outgoing student in college and hostel in BTech.

Felicitated for being the school topper in 12th and 10th and 0.1 percentile in CBSE for two subjects in 10th and 12th.

Published papers in conferences and journals.

Did computer Training to students in Assosiation of People with disability as part of Digital Literacy week

Part of KALVI for teaching less privileged students.

COURSES DONE

- ASIC Design

- Digital Circuit Design, FPGA Based Design

- VLSI Testing and Verification, Scripting and Verification

- Analog IC Design, Low Power Design

- Mixed Signal Design, RFIC Design

PERSONAL DE TAILS

Permanent Address: Pampalil, Near Telephone exchange, Kundara P O, Kollam, Kerala, 691501

Date of Birth : 30th June 1988

Contact this candidate