VerilogHDL, Digital design, C language
Resume:
MANJEET SINGH LOWANSHI
Contact no: 757-***-****
Email id:*******@*****.***
Area(s) of Interest: Digital design/Verification/Validation, Analog design, Digital signal
processing, Fabrication.
Educational Qualifications:
Educational Qualifications Year Board/Institution CGPA*/%
PG (Microelectronics and VLSI) 2014 Indian Institute of Technology (IIT) 6.833
(till 3rd semester). Roorkee
Rungta College of Engineering
UG (Electronics and 2010 65.72
&Technology
communication)
58.2
B.S.P. Senior Secondary School
Intermediate (10+2) 2006
Sector-4,Bhilai
Little Flower Higher Secondary
Tenth 2004 81
School, betul
* On the scale of 10
Projects
M.Tech Dissertation IIT-Roorkee,
Fabrication and Characterization of GaAsMOSCAP(2013-14) (1 year)
Till present scenario semiconductor industry achieved acceptable level of accuracy in silicon technology, but
when it comes to III-V semiconductor, the process used for fabrication of III-V semiconductor based MOSFET
are not up to the mark. Here I have worked to solve problem in this area by growing good quality stable oxide
over GaAs semiconductor and then studied its characteristics. I have calculated interface trap density and
permittivity of the oxide. Also performed the temperature reliability of fabricated device and plotted Arrhenius
plot for calculating activation energy.
B.Tech Project
Rungta college of Engineering and Technology(2010)
RF based ECG (6 months)
RF based ECG is a wireless device which measures heart rate and pulse rate.
A Verilog Simulation of USART
In this project we study the basic structure and behavioural implementation of logic circuits using Verilog codes. We
selected one IC that is Universal synchronous and asynchronous receiver transmitter (USART) and we implement a
behavioural description for transmitter section, receiver section and various logics sections in USART. Finally we
simulated the code with Xilinx tool and we get various waveforms from transmitter and receiver sections for
different test cases and our results are matched with theoretical things.
Internship Information
Steel Authority of India Limited (SAIL)
Summer Training (1 month)
Study of manufacturing process in Steel Authority of India Limited (SAIL) plant located at Bhilai.
Bharat Sanchar Nigam Limited
Summer training (1 month)
Study of basic system architecture used in BSNL Durg.
Extra courses taken
Semiconductor device Physics, MOS devices and modelling, Analog VLSI design, Digital VLSI design, VLSI
Technology, Physical VLSI design, Principles of Microwave, Design of RF and microwave elements, short
course on nano-electronics.
Skills and Achievements
Computer Languages: C(NIIT), VerilogHDL
Software Packages: IC compiler, Xilinx, Visual TCAD, Sentaurus TCAD.
Operation systems: Windows and Linux
Academic Achievements & Experience
In GATE 2011 I got AIR-842 with 99.3percentile
Teaching Assistant for Digital Electronics and semiconductor devices, IIT-Roorkee
Extra-Curricular:
Cricket (2013)
Winner in intra-bhawan and interyear tournament
7th National Science Olympiad (2004)
Certificate of participation
Quiz competition (2005)
Certificate of participation
Blood Donation Camp-IITR (2012): Active donor in the blood donation camp that was held in IIT -Roorkee
Personal Details
Father's Name: S.K. Lowanshi Contact No: 757-***-****
Date of Birth: Dec 1, 1988 Gender: Male
Permanent Address:Qr. No.3/B, St.-37, Sector-4, Bhilai - 490001.
References
Dr. A. K. Saxena
Dr. Sanjeev Manhas
Professor
Associate professor
Indian Institute of
Indian Institute of Technology
Technology Roorkee
Roorkee
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