Design Engineering

Nithya Sree Thiruvalluru,

**-*-****, ****** ****** Hospital,

Muthukur Road, Nellore,

Email: ******************@*****.***

Andhra Pradesh-524 003.

Mobile: +91-779*******

Summary of Qualifications:

. Good understanding of the ASIC and FPGA design flow.

. Extensive experience in writing RTL models in Verilog HDL and

Testbenches in SystemVerilog and UVM.

. Very good knowledge in verification methodologies.

. Experience in using industry standard EDA tools for the front-end

design and verification.

VLSI Domain Skills:

HDL: - Verilog

HVL: - SystemVerilog

Verification Methodologies: - Coverage Driven Verification

Assertion Based Verification - SVA

TB Methodology: - UVM

Protocols: - SPI

EDA Tool: - Questasim and ISE

Domain: - ASIC/FPGA front-end Design and

Verification

Knowledge: - RTL Coding, FSM based design,

Simulation,

Code

Coverage, Functional Coverage, Synthesis,

Static

Timing Analysis, ABV- SVA

Qualification:

Maven Silicon Certified Advanced VLSI Design and Verification course:

From Maven Silicon VLSI Design and Training Center, Bangalore

Feb. 2014 - July 2014.

Bachelor of Technology:

Priyadarshini Institute of Technology, Nellore.

Affliated to JNTU, Andhra Pradesh, India

Discipline: Electronics & Communication Engineering

Percentage: 80%

Year: 2009-2013

Intermediate:

Narayana Junior college, Nellore.

Percentage: 96%

Year: 2007-2009

VLSI Projects:

1. Router 1x3 - RTL design and Verification

HDL: Verilog

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Questasim and ISE

Description: The router accepts data packets on a single 8-bit port

and routes them to one

of the three output channels, channel0, channel1 and channel2.

Responsibilities:

. Architected the design.

. Implemented RTL using Verilog HDL.

. Architected the class based verification environment using system

Verilog.

. Verified the RTL model using SystemVerilog.

. Generated functional and code coverage for the RTL verification sign-

off.

. Synthesized the design.

2. SPI Core Verification

HVL: System Verilog

TB Methodology: UVM

EDA Tool: Questasim

Description: The SPI IP core provides serial communication

capabilities with external

device of variable length of transfer word. This core can be

configured to connect with 8

slaves.

Responsibilities:

. Architected the class based verification environment in UVM.

. Verified the RTL module using System Verilog.

. Generated functional and code coverage for the RTL verification sign-

off.

3. Engineering Project

Design and simulation of UART serial communication module based on

Verilog during

final year of B.Tech.

Personel Traits:

. Self motivating capability.

. Positive Attitude in every aspect.

. Ability of Team Management.

Achievements:

. Stood first in Elocution Competition held by Election Commission of

India on the Occasion of Voter's day at college level in 2011.

. Participated in Work shop held by ISRO(Bangalore) on Satellite

Navigation and Aviation at SVU,Thirupathi.

Interests:

. Interested in Dance and making craft works.

. Provinding services through EYES Organization

Declaration:

I hereby declare that the information and facts furnished

here are true to the best of my knowledge and belief.

Place:Bangalore

Date:

( T.Nithya Sree )

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