Engineering Project

RESUME

M.Prashanthi

M.Tech: Electronics

Pondicheery University

Pondicherry – 606014, India,

**********@*****.***

Objective:

To be associated with a research group, which provides career development opportunities

where innovation and new ideas are nurtured and contribute in its progress through my

knowledge and capable of achieving objectives through committed work.

Course University Institute Year CPI/%

Post-Graduation Pondicherry University Pondicherry University 2014 8.8

Undergraduate Specialization: Electronics and Communication Engineering

Graduation JNTUH ATRI 2011 71.07

Intermediate/+2 BIE Little Flowers Junior College 2007 78.70

St Joseph’s Public School

Matriculation ICSE 2005 66.67

Key Achievements:

o Gate 2014 qualified

o

Published a paper on “An Enhanced (15,5) BCH Decoder using Verilog

HDL”, International Journal Advanced Research in Computer and Communication

Engineering, vol. 2, no.11, pp. November 2013, ISSN (Print) : 2319-5940. Impact

Factor: 1.770.

o M. Prashanthi and P. Samundiswary," An Area Efficient (31, 16) BCH Decoder for

Three Errors", International Journal of Engineering Trends and Technology (IJETT) –

Volume 10 Number 13 - Apr 2014

o M. Prashanthi, Damarla Paradhasaradhi and N Vivek, “An Advanced Low Complexity

Double Error Correction of an BCH Decoder”, IEEE International Conference on Green

Computing, Communication and Electrical Engineering, March-2014(under Publication).

o Damarla Paradhasaradhi, M. Prashanthi and N Vivek, “A Modified Wallace Tree

Multiplier using Efficient Square Root Carry Select Adder”, IEEE International Conference

on Green Computing, Communication and Electrical Engineering, March-2014 (under

Publication).

Academic Projects :

M. Tech Main Project:

1. An Enchased Chase BCH Decoder

Error-correction codes are the codes used to correct the errors occurred during the

transmission of the data in the unreliable communication mediums. The idea behind these codes is

to add redundancy bits to the data being transmitted so that even if some errors occur due to noise

in the channel, the data can be correctly received at the destination end. Bose, Ray- Chaudhuri,

Hocquenghem (BCH) codes are one of the error-correcting codes. The BCH decoder consists of

four blocks namely syndrome block, IBM block, chien search block and error correction block.

This paper describes a new method for error detection in syndrome and chien search block of

BCH decoder. The proposed syndrome block is used to reduce the number of computation by

calculating the even number syndromes from the corresponding odd number syndromes. The new

factorization method used to implement the algorithm of chien search block of enhanced BCH

decoder reduces the number of components required. Thus, a new model of BCH decoder is

proposed to reduce the area and simplify the computational scheduling of both syndrome and

chien search blocks without parallelism. The enhanced chase BCH decoder is designed using

hardware description language called Verilog and synthesized in Xilinx ISE 13.2.

2. Design and Study of an Enhanced BCH Decoder for Four Errors

This project presents a low-complexity and area efficient error-correcting BCH decoder

architecture for detecting and correction of three and four errors. The advanced Peterson error

locator computation algorithm, which significantly reduces computational complexity, is

incorporated in the IBM block of (15, 5) and (31, 16) Enhanced BCH decoder. In addition, an

advanced BCH Decoder (63, 39) for 4 errors is developed with modified enhanced syndrome,

chien block and Modified Direct Solution Algorithm is used for finding o ut the co-efficient of the

error locator polynomial in the IBM block, thus resulting in the less hardware complexity and area

efficient BCH decoder which can correct four errors. These BCH decoders are designed using

hardware description language called Verilog and synthesized in Xilinx ISE 13.2.

B.Tech Project: Microcode and FSM based memory Built-in-self test for coupling fault detection

(VLSI)

Defects in memory arrays are generally due to shorts and opens in memory cells, address

decoder and read/write logic. These defects can be modeled as single and multi cell memory

faults. Application of test sequences to embedded memories using off-chip testers results in a high

test time and test cost due to the large size of embedded memories. To overcome this pr oblem, the

computed test sequences are generated on-chip using a memory Built-in Self Test (BIST) unit.

Mini Project: Brake Failure Indicator

Technical Skills:

Programming: C, Java, Verilog, vhdl,basics of matlab,

Software Packages: Xlinx, Tanner.

Extracurricular Activities:

Attended CADENCE workshop held at Model Engineering College, Thrikkakara,

Ernakulam.

IEEE member for one year

Participated in Inter-Department Cricket Tournment in Pondicherry University.

Participated in The Institution Of Engineer and MWIPWCM workshop held at Pondicherry

University.

Personal Details:

Name : M.Prashanthi

Father’s name : M.venkateshwar

Alternative E-Mail Address : ***********@*****.***

Date of Birth : 19 august 1990

Nationality : Indian

Languages Known : English, Hindi and Telugu

Hobbies : listening music, watching TV

References:

P. SAMUNDISWARY

Assistant Professor,

Department of Electronics Engineering

School of Engineering & Technology

Pondicherry University,

Pondicherry – 605 014

Email: ****************@*****.***

Mobile No: 094********

Dr.R.Nakkeeran

Head of the Department

Department of Electronics Engineering School of Engineering and Technology

Pondicherry University

Puducherry 605 014

Email: *********.***@********.***.**,****.***@********.***.*************@gmail.com

Mobile No: +91-919*********

Declaration:

I solemnly affirm that the above furnished particulars are true to the best of my knowledge and

belief.

DATE: 30-8-2014

PLACE: PONDICHERRY (M.Prashanthi)

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