Engineering Project

P.C.Rajitha kumari

Mobile: +91-990******* E Mail : *.*.*********@*****.***

Objective

An enthusiastic, flexible individual seeking a challenging career in a progressive organization that gives me an

option to apply my knowledge and skills.

Summary

Exceptionally talented Engineer with Post Graduate Diploma in VLSI design and good academic record.

Committed to the highest levels of professionalism and excellent interpersonal skills. Demonstrated expertise in

Verilog HDL and front end Cadence based ASIC flow with industry standard project work. Seeking a challenging

role in ASIC design.

Skills Summary

1. HDL Coding, Verilog 5. Cadence Tool Suite 9. Linux

2. Logic Design 6. RTL Complier 10. Simvision

3. Finite State Machine 7. NCVERILOG 11. XILINX ISE

4. Synthesis 8. Physical Design

(ASIC Flow)

Project Experience

MINI PROJECTS – ADVANCED DIPLOMA IN VLSI DESIGN

8 Bit Serial ALU Design

Sequential Multiplier Design

Digital Clock

Stop watch

Major Project – B.Tech Electronics & Communication Engineering

BLOCK ARTIFACT REDUCTION SCHEME USING PSEUDO RANDOM NOISE MASKING

Major Project – M.Tech VLSI Design

A CONCURRENT ONLINE FAULT DETECTION, DIAGNOSIS AND REPAIR USING RANDOM

PATTERN GENERATOR

P.C.Rajitha kumari

Paper presented & workshop

Presented a paper on a Topic “A Concurrent Online Fault Detection, Diagnosis And Repair Using

Random Pattern Generator”.International Conference on Futuristic Trends in Electronics Engineering at

Thiruvalluvar College of Engineering and Technology, Vandavasi.

Attended Two days national Workshop on “RF& Microwave Technologies and its Applications”

Conducted by Kamban Engineering College.

Attended Work Shop on “FPGA Programming for Beginners”.TIFAC CORE in AUTOMOTIVE

INFOTRONICS at VIT University, Vellore.

Education

INDIAN INSTITUTE OF VLSI DESIGN & TRAINING–Bangalore, Karnataka

Post Graduate Diploma in VLSI Design & Technology, March 2014

Six Month Full Time Course in ASIC Design based on Cadence flow. Course work included 150 hours of theory

and 200 hours of lab work including industry standard project work.

M.E. –VLSI Design (2011 2013) in Arunai College of Engineering, Thiruvannamalai.CPGA: 7.9

B.E in Electronics and Communication Engineering(2007 2011) in Thiruvalluvar College of Engineering

and Technology. Percentage: 69.

HSC (2006 2007) in Thiruvalluvar Higher Sec. School, Gudiyatham. Percentage: 67

SSLC(2005) in Desia Matric Higher Sec. School, Vellore. Percentage:75

Personal Details

Father’s name : Mr.CHINNAMA REDDY P.

Date of Birth : 12.09.1989

Gender : Female

Marital status : Single

Nationality : Indian

Linguistic Proficiency : English, Telugu, Tamil

DECLARATION

I hereby declare that the above said information is true to the best of my knowledge and belief.

Thanking you,

Yours Sincerely,

P.C.Rajitha kumari

Place: Bangalore (P.C.Rajitha

kumari)

Date:

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