Engineer Project

APURVA NIWAS PATIL

Mobile no.: +91-942******* Email: ***********@*****.**.**

Career Objective

To seek a position of entry level engineer in the field of VLSI

digital design/Physical design/Verification

Summary

. Experience in verification aspects like writing test cases using

System Verilog, RTL simulation and gate level simulation (with and

without SDF) using NC-Sim

. Experience in Formal verification using cadence conformal LEC tool

. Good knowledge in Digital design, RTL design using Verilog, basic SoC

design flow and basics of cmos

. Familiar with basics of Low power design methodology and STA concepts

. Knowledge of Scripting languages like TCL, Perl

. Good analytical and problem-solving skills, eager and quick learner

with team-work spirit

Educational Qualification

. Master of Technology in VLSI and Embedded system from College of

Engineering Pune with CGPA 9.46/10 in 2014

. Bachelor of Engineering in Electronics and Telecommunication

Engineering from Pune University with 78.97% in 2011

. HSC Maharashtra State Board with 90.17% in 2007

. SSC Maharashtra State Board with 85.46% in 2005

Internship

LSI Research & Development Pvt. Ltd., Pune 3rd July 2013 -30th June

2014 (1 year)

1. Test mode verification

Description : Test mode logic is the extra logic added on SoC for

validating and testing embedded IPs at SoC level. Test mode

verification team plays a supporting role in SoC validation, testing

and debugging. Being a part of test mode verification team, my task

was to write and simulate the test cases at various design stages, for

testing IP features at SoC level and for verifying implementation of

test mode logic and to generate test vectors for post silicon

validation of IPs at SoC level. The SoC, on which I worked, was a

flash controller SoC with 8 hard macros which were our targeted CUTs.

Responsibilities :

. To write System Verilog based test cases in order to check targeted

features of

IPs at SoC level along test mode path

. To simulate test cases on RTL and debug the issue

. To simulate and debug netlist without SDF

. To simulate and debug postlayout netlist with timing using SDF

. To generate and validate the test vectors for IP centric post

silicon validation

2. Formal verification

Description : In formal verification, I owned the task of carrying out

logical equivalence check on flash controller SoC which was a live

project of the company. I carried out the equivalence check on block

level, partition level and on whole SoC. I have experience in flat,

hierarchical, low power aware equivalence check and debugging LEC

issues. I wrote automation Scripts for conformal LEC tool.

Responsibilities :

. To carry out Formal verification on flash controller SoC using

cadence conformal LEC tool from RTL to prelayout stages for all the

design phases.

. To carry out Low power aware Formal verification on flash

controller SoC.

. To debug various LEC issues

. To write automation scripts for conformal LEC tool

Academic Courses

1. Webinars on Low Power VLSI Design Jan2013 - March2013

(3months)

. Successfully completed short duration course on Low Power VLSI

Design by Dr.Bhanu Kapoor, consultant/owner, Mimasic held at COEP.

2. Academic Course on VLSI Design and Verification

July2012 - Dec2012

. Successfully completed academic course on VLSI Design and

Verification held at COEP conducted by Intel.

. Designed FIFO, memory read-write controller using Verilog HDL and

developed test bench using System Verilog

Academic Projects

Graduation Major Project : e-chair July2010

- June2011 (1 year)

. The objective of this project was to develop a motorized wheelchair

which is operated using touch screen and equipped with sensors to

provide safety, comfort and ease to move to the motion impaired

people.

Graduation Mini Project : Gesture Translator Dec 2009 - May 2010

(6 months)

. The objective of this project was to develop, a smart glove that can

recognize basic hand gestures of mute person and convert them into

text.

Technical Skills

Technical : Verilog, VHDL, System Verilog, TCL, Perl, basic C

Languages

Tools : NC-Sim, Conformal LEC tool

Achievements and Extra-curricular Activities

. Presented paper and got excellent paper award in ICEECE international

conference by IRAJ held in April 2014.

. Stood 3rd in All India intern presentation contest at LSI 2013.

. Participation in International VLSI and Embedded System conference at

Pune January 2013.

. Cleared GATE examination 2011 with all India rank 1557 (98.87

percentile)

. Have topped in college consistently each year.

. Participated in NSS camp and various activities like sports, dance in

college cultural events.

Personal Profile

Date of Birth : 18th June 1989

Residential : 19, Gururaj Housing Society, Near Krishna

address Hospital, Paud Road, Kothrud, Pune - 38.

Languages known : English, Marathi, Hindi

Date :

Place : Pune (Apurva N. Patil)

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