physical design engineer
Resume:
T.VENKAT RAG HAVA Email:
****************@*****.***
Mobile: +91-
OBJECT I V E:
Seeking a challenging and enduring job in professional organization where my skills & abilities could
be fully utilized to achieve organizational goals and professional growth.
E D UCAT IO NAL QUAL I F ICAT IO NS:
B.Tech w ith discipline E lectronics & Communication Engineering w ith an aggregate of 60% in 2010
f rom Sri Sai Jyothi College of Engineering affiliated by JNTU, Hyderabad.
Intermediate w ith an aggregate of 85% in 2006 from Takshashila Junior College, A.P.
SSC w ith an aggregate of 75% in 2004 from D.A.V High School, A.P.
PROFESSIONAL EXPER I ENCE :
1.2 years as intern in Physical Design Engineer in “OPTIM IST SOFTECH” .
PROFESSIONAL TRA I N I NG:
U ndergone intensive t raining in VLSI PHYSICAL DESIGN from Institute of Silicon Systems Pvt L td.,
H yderabad.
COURSE OUT L I NE:
V LSI Fundamentals, CMOS Basics, Digital Design, Floor Planning, Power Planning, Placement and
Routing, clock t ree synthesis, static timing analysis timing optimization, cross talk analysis, IR Drop
A nalysis and Physical Verification.
EDA Tools Used :
SOC Encounter : F loor Plan, Place and Route, Clock Tree Synthesis
RTL Compiler & ETS : Logic Synthesis & Static Timing Analysis
ETS-Celtic : Signal Integrity & IR drop Analysis.
QRC : RC-Extraction
Virtuoso LE : Standard Cell Layout Designing
PROJECT P rofile :
P roject 1:
BLOCK1
Technology : 45nm, 11 Layer Metal, Multi-Vt Libraries
Tools : SOC Encounter, ETS
Instance : 800K
Hard Macros : 16
Frequency : 500MHz
Responsibilities: I am responsible for Block level Floorplanning, Power planning, DeCap
i nsertion, Placement Driven Synthesis, Post placement Timing closure, Clock Tree Synthesis,
C lock wiring, Post clock Timing closure, clock slew fixing, Set-up and Hold Fixing on Prewired
database, Timing driven and SI driven Routing, Post Route Timing fixing, Fixing DRCs.
P roject 2 :
BLOCK1
Technology : 65nm, 10 Layer Metal, Multi-Vt Libraries
Tools : SOC Encounter, QRC, ETS
Instances : 600K
H ard Macros : 40
Frequency : 500MHz
Responsibilities: I am responsible for Block level Floorplanning, Power planning, DeCap
i nsertion, Placement Driven Synthesis, Post placement Timing closure, Clock Tree Synthesis,
C lock wiring, Post clock Timing closure, clock slew fixing, Set-up and Hold Fixing
on prewired database, Timing driven and SI driven Routing, Post Route Timing fixing, Fixing DRCs.
P roject 3 :
BLOCK (GMAC):-
Objective : T iming Driven Layout
Tools : SOC Encounter, QRC & ETS.
Macros / Cells / IOs : 12 / 25207 / 120
No. of Clocks : 17
F requency : 200 MHz
Technology/Layers : UMC 0.13 micron / 5 Metal Layers
Role: Performing sanity check, Design import, Floor Plan, Power Plan, Placement, IPO, congestion
estimation with Trial Route, CTS, Adding Filler Cells, detail route, RC Extraction, Timing analysis,
ECO’S.
BLOCK (USB-WRAPPER):-
Objective : T iming Driven Layout
Tools : SOC Encounter,QRC & ETS.
Macros /STD Cells : 12/26640
No. of Clocks :4
Frequency : 150MHz
Technology/Layers : CSM 0.18 micron/5 Metal Layers
Role: Performing sanity check, Design import, Floor Plan, Power Plan, placement, IPO, congestion
estimation with Trial Route, CTS, Adding Filler Cells, detail route, RC Extraction, Timing analysis,
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T.VENKAT RAG HAVA Email:
****************@*****.***
Mobile: +91-
ECO’S.
PROJECT.4:-
Objective : Timing Driven Layout
Tools : SOC Encounter & ETS.
Macros /STD Cells : 12/25195
No. of Clocks : 17
Frequency : 200MHz
Technology/Layers : TSMC 0.13 micron/5 Metal Layers
Role : Performing sanity check, Design import, Floor Plan, Power Plan, placement,
I PO, congestion estimation with Trial Route, CTS, Adding Filler Cells, detail route, RC Extraction,
T iming analysis, ECO’S.
ACADE M I C PROJECTS
PROF I LE#1
Title : I mplementation of Heart Beat Monitoring Using DWT
Role : Team Leader
Tool : M at lab
Description : The aim of the ECG simulator is to calculate heart beat of ECG waveforms.
T his monitoring system is developed on mat lab using discrete wavelet t ransformation technique .In
t his project we explained the importance of heart beat monitoring the way we detect the ECG signals
by using Discrete Wavelet Transform.
PROF I LE#2
Title : GSM Based Pick and Place Robot
Role : Team Leader
Tool : Implemented using Microcontroller 8051.
Description : The pick and place robot is a microcontroller based mechatronic system that
p icks the object from source location and places at desired location.
Whole process is controlled by a microcontroller. A GSM modem is used for controlling the robot
moments, thus enabling the system to be controlled remotely.
STRENGTHS
Good discipline, t ime management and goal orientation.
Handling the given task effectively with in given time.
Quality Oriented Mind setup & Flexible to take up any kind of responsibilities.
(T.Venkat Raghava)
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