Design Project

G.MANI KANTA

Mobile: +91-740*******, E-Mail:

*.************@*****.***

OBJECTIVE: To obtain a challenging position of physical design engineer

that offers opportunity for advancement and personality development and

fully utilizes in an environment, where I would learn and improve myself

and thus be an asset to the organization

Training period: Undergone training in VLSI Design at Bangalore from SION

Semiconductors

Since July2013 to December2013.

Training Details: CMOS Fundamentals, Digital Design.

Physical Design: VLSI Flow, Floor-Plan, Power Planning, Placement and

Routing, Static Timing Analysis, Clock Tree Synthesis, IR Drop Analysis and

Physical Verification.

AREA OF EXPOSURE:

. Exposure in Physical Design

. Exposure to Synthesis

TECHNICAL SKILLS:

. PNR Tool : Cadence SOC Encounter.

. Synthesis : Synopsys-Design Compiler.

. HDLs : Verilog, VHDL.

. Technologies : 90nm, 130nm.

EDUCATIONAL QUALIFICATIONS:

Examination Institute University/Board Year of Aggregate/Percentage

passed studied passing

Simhadhri J.N.T.U University, 2009-13

B.Tech Engg. College, Kakinada 60.70%

(E.C.E) Visakhapatnam.

Intermediate Sri Chaitanya 2007-09 86.20%

Junior Board of

College, Intermediate

Visakhapatnam. Education

X STD Sri Prakash SSC 2007 88.33%

vidya niketan,

P.R.peta

Visakhapatnam

AREA OF INTEREST:

. Physical Design

. Synthesis

. Digital logic Design

. RTL coding

PROJECT PROFILE:

SYNTHESIS PROJECT

Objective: Implementation of Alarm Controller Project using Synopsys DESIGN

COMPILER.

Responsibility: Responsible for taking the design through Specify

libraries, Read design, Define Design Environment, Set Design Constraints,

Optimize the Design, Analyze and Resolve the Design Problems and Report

generation.

PNR Project 1

Objective: Timing Driven Layout Using 42 Macros ON 90nm TECHNOLOGY.

Tools : SOC Encounter.

Gate count : 50,414

Blocks : 42

No. of Clocks : 01

Frequency : 500 MHz

Responsibility: Responsible for taking the design through floor planning,

placement, Clock Tree Synthesis and Routing.

Issues Resolved :Performing sanity check, Design import, Floor Plan, Power

Plan, Placement, resolving timing issues, Trail Route, Power analysis,

Timing analysis, Adding Filler Cells, Timing analysis.

PNR Project 2

Objective: DTMF CHIP Using 25 Macros ON 130nm TECHNOLOGY.

Tools : SOC Encounter.

Gate count : 56,052

Blocks : 25

No. of Clocks : 01

Frequency : 500 MHz

Responsibility: Responsible for taking the design through floor planning,

placement, Clock Tree Synthesis and Routing.

Issue Resolved :Performing sanity check, Design import, Floor Plan, Power

Plan, Placement, Resolving timing issues, Trail Route, Power Analysis,

Timing Analysis, CTS, Adding filler cells.

Extracurricular Activities:

. Act as a organiser for my department conducting "TECH AARON" national

level fest.

. Achieved second place in table tennis competition at central level.

. Achieved second place in drawing competition conducted by KALA BHARATI

AUDITORIUM at school.

. Participated in one day workshop on "EMBEDDED SYSTEMS" conducted by

"SIMHADRI EDUCATIONAL SOCIETY GROUP OF INSTITUTIONS".

STRENGTHS:

. Strong technical acumen and Valuable team player, while keeping

abreast with latest technologies.

. Self-directed, highly driven, enthusiastic about work, strong will to

be successful, committed to continuous improvement of skills and very

ambitious to help others.

. An effective communicator with honed relationship management,

analytical, logical and problem-solving abilities.

. Willingness to learn, Team facilitator.

PERSONAL SNIPPETS:

Name : G.MANI KANTA

Father's Name : G.RAMA KRISHNA

Mother's Name : G.SUJATHA

Date of Birth : 20/09/1991

Personal Interest : Surfing internet, watching

scientific fiction movies.

Languages Known : English, Telugu.

DECLARATION:

I hereby declare that the above mentioned information is correct up to my

keen and I bear the responsibility for the correctness of the above-

mentioned particulars.

Place : Bangalore

Date :

(G.MANI KANTA)

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