Project Design

MUNNANGI LAVANYA

Home Address:

Munnangi Lavanya,

Bank colony, prasanth nagar,

E-mail:***********@*****.***

Uppal, Hyderabad.

ph.No: 833*******, 829-***-****.

OBJECTIVE

To work in an organization that will utilize and enhance my skill

sets in the field of, VLSI front end (ASIC/FPGA) designing, Verification

and applications. To achieve excellence, to be resourceful and optimistic

and to pursue a challenging career in VLSI design.

EDUCATION

. M.TECH, VLSI System Design, Anurag Cvsr College of Engineering,

Hyderabad, 2014, with 84%.

. B.Tech, Electronics and Communication Engineering, Lakireddy

Balireddy College of Engineering, Mylavaram, 2012 with 79.64%.

TOOLS AND LANGUAGES

. Hardware Description Language : VHDL, VERILOG, SYSTEM VERILOG.

. Design Tools : Modelsim, XILINX ISE.

. FPGA : SPARTAN 3.

. Physical design tools : LT-SPICE, ELECTRIC TOOL,

CADENCE.

. Languages : C, C++, PERL.

. Processor : 8086, 8085 Assembly

language.

. Operating system : LINUX, WINDOWS.

TECHNICAL SKILLS

. Thorough knowledge of RTL Design concept from anything ranging from RTL

to Synthesis.

. Comprehensive understanding of methodologies of RTL Description,

simulation Behavior Model and synthesis issues.

. Beginner in Systemverilog.

. Familiar with ASIC Front-end Design Methodologies and verification

flows.

. Proficient in Modelsim (Mentor graphics) and Xilinx ISE EDA tools

. Hand on experience of developing various Projects on VHDL and Verilog-

HDL.

PROJECT DETAILS

. Project : DESIGN OF MODIFIED LOW POWER BOOTH MULTIPLER.

Description: The design of normal multiplier consumes most of the power in

DSP processors.

Tools : XILINX ISE 14.4, MODELSIM.

Languages : VERILOG, VHDL.

. Project : DESIGN OF LOW POWER HIGH SPEED TRUNCATION ERROR TOLERANT

ADDER and its application in DSP.

Description : The data processed by many digital systems may already

contain errors.

Tools : XILINX ISE 14.4, MODELSIM.

Languages : VERILOG, VHDL.

. Project : An Efficient SQRT Architecture of Carry Select Adder

Design by Common Boolean Logic.

Description : Carry Select adder (CSLA) is known to be the fastest

adder among the Conventional adder structures.

Tools : XILINX ISE 14.4, MODELSIM.

Languages : VERILOG, VHDL.

. Project : Design and implementation of MAC unit using reversible

logic.

Description: For irreversible circuits, losing one bit of information

dissipates (kTln2) joules of heat energy, where k is Boltzmann's

constant and T is the absolute temperature.

Tools : XILINX ISE 14.4, MODELSIM.

Languages: VERILOG, VHDL.

STRENGTHS

. Strong Interpersonal and Communication skills.

. Determination, dedication, and discipline.

. Willing to learn and adapt to new opportunities and challenges.

LANGUAGES

. I am fluent in English and Telugu (written and spoken), Hindi.

DECLARATION

I hereby declare that the information furnished above is

true and correct to the best of my knowledge and belief

Place:

(M.Lavanya)

Date:

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