Design Project
Resume:
SRINIVAS.ETTAMSETTY
Babuji Nagar, Near Rythu bazar,
Email:********.****@*****.***
Gopalapatnam, Visakhapatnam,
Mobile: +91-903*******
Andhrapradesh, India - 530027
Summary of Qualifications
> Good understanding of the ASIC and FPGA design flow
> Experience in writing RTL models in Verilog HDL and
Testbenches in System Verilog.
> Sound knowledge in verification methodologies
> Experience in using industry standard EDA tools for the front-end
design and verification
VLSI Domain Skills
HDLs: Verilog and VHDL.
HVL: System Verilog.
Verification Methodologies: Coverage Driven Verification
Assertion Based Verification
TB Methodology: UVM.
EDA Tool: Modelsim and ISE
Domain: ASIC/FPGA Design Flow, Digital Design
methodologies
Knowledge: RTL Coding, FSM based design, Simulation,
Code Coverage, Functional
Coverage, Synthesis,
Static Timing Analysis,
ABV.
Professional Qualification
Maven Silicon Certified Internship
From Maven Silicon VLSI Design and Training Center, Bangalore
Year: August 2013
Maven Silicon Certified Advanced VLSI Design and Verification course
From Maven Silicon VLSI Design and Training Center, Bangalore
Year: June 2013
Bachelor of Engineering, Dadi institute of engineering and
technology,Visakhapatnam JNTU
university, Kakinada,Andhra Pradesh, India
Discipline: Electronics and
Communication Engineering
Percentage: 66% First class.
Year:
July 2012.
Hsc : 83%
Ssc : 79%
VLSI Projects
Real Time Clock - RTL design and verification
HDL: Verilog
EDA Tools: ISE
> Implemented the Real Time Clock using Verilog HDL independently
> Architected the class based verification environment using
SystemVerilog.
> Verified the RTL model using SystemVerilog.
> Generated functional and code coverage for the RTL verification sign-
off
> Synthesized the design
Dual Port RAM - verification
HVL: System Verilog
EDA Tools: Modelsim, Questa - Verification Platform and ISE
> Implemented the Dual Port Ram using Verilog HDL independently
> Architected the class based verification environment using system
Verilog
> Verified the RTL module using System Verilog
> Generated functional and code coverage for the RTL verification sign-
off
Router 1x3 - RTL design and Verification
HDL: Verilog
HVL: SystemVerilog
TB Methodology: UVM.
EDA Tools: Modelsim, Questa -- Verification Platform and ISE
Description : The router accepts data packets on a single 8-bit port called
data and routes the packets to one of the three output channels, channel0,
channel1 and channel2.
> Architected the design and described the functionality using Verilog
HDL.
> Architected the class based verification environment using system
Verilog
> Verified the RTL model using SystemVerilog.
> Generated functional and code coverage for the RTL verification sign-
off
> Synthesized the design
AHB-TO-APB BRIDGE
TB Methodology: UVM.
EDA Tools: Modelsim.
The AHB TO APB BRIDGE consists of a AHB slave, a APB controller and various
control and status registers. This BRIDGE can operate in 8-bit data bus
mode, 16-bit data bus mode or in 32-bit bus mode. The BRIDGE is between AHB
and APB protocols, which are AMBA buses, which includes the synchronization
between high frequency AHB bus and low frequency APB bus. It is a one-to-
one connection between single AHB bus and single APB bus.
> Designed RTL using Verilog.
> Verified the RTL module using Universal verification methodology.
UART- IP Core - Verification
TB Methodology: UVM.
EDA Tools: Modelsim.
The UART IP core consists of a transmitter, a receiver, a modem interface,
a baud generator, an interrupt controller, and various control and status
registers. This core can operate in 8-bit data bus mode or in 32-bit bus
mode, which is now the default mode. It is an interface between wishbone
compatible UART transceiver, which allows communication with modem or other
external devices, like another computer using a serial cable and RS232
protocol. The UART core RTL is technology independent and fully
synthesizable.
> Architected the class based verification environment using system
Verilog
> Verified the RTL module using Universal verification methodology.
> Generated functional coverage for the RTL verification sign-off
Engineering Project
TITLE: DATA EMBEDDED IN A SCRAMBLED DIGITAL VEDIO
Description: This project involves the technique of encryption of the data
and scrambling the encrypted data.This technique successfully completed on
AVI format.Main aim of this project to provide security.This technique
generally used to provide confidential communication,used in military for
secret communication and data hiding over authorized web pages.
Technologies used: Front-End : MAT LAB
Environment : Digital signal
processing
Declaration
I here by declare that the above information provided is true as far as
best of my knowledge
(ETTAMSETTY.SRINIVAS)
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