CURRICULUM VITAE

NAME: MAHENDRA KUMAR MD

Email : aceyzb@r.postjobfree.com No 45,Ist Phase,

IInd Stage,IIIrd cross,

Contact no : +91-886******* Chandra layout,Vijaya nagar

Bangalore -560040.

Objective

An enthusiastic and self-motivated experienced Physical design engineer

looking for a challenging and responsible position as Physical design

engineer to apply my knowledge and skill with my hard work and patience,

and be world class in ASIC design.

Summary

* Expertise in Synthesis, Static timing analysis, Floor Planning, Power

Planning and Placement

* Expertise in Clock tree synthesis, Routing

* Expertise in Physical verification

* Experience in various technologies - 90nm, 180nm

Skill & tools

Technical: ASIC Design & Verification, HDL Coding, Verilog, CADANCE tool

suite, RTL Compiler, NCVERILOG, Simvision, Virtuoso, Xilinx 14.1 (ISE

Design Suite Digital & Analog Circuit Design, ModelSim, FPGA, Synthesis &

DFT using RC-compiler, ASIC (Back-End) Physical Design using Soc Encounter.

Language: C, C++, Shell and Perl scripting.

OS: Windows 7, Windows XP and LINUX

* RTL Coding : Verilog and VHDL

* Synthesis : RTL Compiler

* Physical Implementation : SOC Encounter

* Physical Verification : Assura

* Scripting Languages : Basic knowledge in PERL

* Parasitic extraction : RC Extractor

Projects

Project 1: Block level

Objective : Optimize for timing as well as for power

Tools : SOC Encounter, QRC, ETS

Gate count / Area : 356,296 / 1,886,801.9 um2

Macros / STD Cells : 8 / 25195

No. of Clocks : 6

Frequency : 400 MHz

Utilization : 70%

Technology / Layers : TSMC 0.18 microns / 6 Metal Layers

Role:

> Floor Plan, Power Plan, Placement, IPO, Trial Route, Pre-CTS

optimization.

> Timing Analysis, CTS, Detail Routing.

> RC extract, STA.

> Started the Design with 70% utilization. Completed the initial pnr

run to get the scaling factors. Building the CTS is critical. After

CTS gets the Clock Gating setup timing violations & to fix those

implemented the CTS with macro model concept & Clock grouping. DRC

violations at the Macros Pins (dropping the via on the via blockage)

for which manual effort needed. Closed the timing in ETS with timing

ECOs.

Project 2: Physical Design & Verification of DTMF Chip

Objective : To do the floor planning, Power planning,

placement, CTS,

Routing, Design signoff,

Generating GDS II.

Tools : SOC Encounter, RTL Compiler

Gate count / Area : 6K

No. of Clocks : 2

Macro count : 4

Frequency : 125 MHz

Utilization : 70.1 %

Technology / Layers : TSMC 0.18 microns / 6 Metal Layers

Role:

> Floor Plan, Power Plan, Placement, IPO, Trial Route.

> Timing Analysis, CTS, Detail Routing.

> To observe the relation between core utilization, wire length and

number of metal layers

Project 3: Physical Design & Verification of FIR FILTER

Objective : To do the floor planning, Power planning,

placement, CTS,

Routing, Design signoff,

Generating GDS II.

Tools : SOC Encounter, RTL Compiler

Gate count / Area : 3K/461504.46 um2

No. of Clocks : 2

Macro count : 0

Frequency : 125 MHz

Utilization : 70.1 %

Technology / Layers : TSMC 0.18 microns / 6 Metal Layers

This project is targeted to 180nm @ 125MHz system clock it's a flatten

design

Responsibilities:-

. Library preparation.

. Synthesis according to the constraints

. STA and DFT

. Involved in good Floor Planning & Power Planning

. Executing the chip P&R starting from floor plan to GDS

MTech -Signal Processing &VLSI

Major Project: AREA AND POWER EFFICIENT CORDIC USING MICRO ROTATION

Project description:

The coordinate rotation digital computer (CORDIC) algorithm is well known

iterative algorithm for performing rotations in digital signal processing

applications. In this proposed work presents an Area-power efficient CORDIC

technique that completely eliminates the scale-factor. By suitable

selection, the order having approximation of Taylor series the proposed

CORDIC circuit meets the accuracy requirement, and attains the desired

range of convergence. Besides we have proposed an generalized micro-

rotation selection technique based on high speed most-significant-1-

detection obviates the complex search algorithms for identifying the micro-

rotations.

HARDWARE USED: FPGA Spartan 3 kit .

SOFTWARES USED: XILINX 14.1,ModelSim 10.0a

B.E- Telecommunication Engineering

Major Project: EXYPNOS OFFICE

Project description:

Major Project based on sensors, computers, LAN to automate the whole office

environment. The project identifies the employee entering the office and,

it greets the employee with his name and the login time, it intimates the

user with the schedules for the day through the SMS. It boots computer

automatically and will turn of the computer when the employee logs off.

HARDWARE USED: PIR sensors, RF receiver-transmitter, RFID, PIC

microcontrollers

SOFTWARES USED: Java, Symbian C++

Role :

. Had taken up the management of project and hardware implementation.

. Technical problem faced during the project development and its

correction been handled.

Education

* PG Diploma in VLSI ASIC Design from IIVDT, Bangalore ( Feb 2014)

Six Month Full Time Course in ASIC Design based on Cadence flow.

Course work included 150 hours of theory and 200 hours of lab work

including industry standard project work.

* MTech in Signal processing and VLSI from SBMJCE, Bangalore with 80%

(Aug 2013)

* BE in Tele Communication Engineering from AMCE, Bangalore with 56%

(July 2011)

Personal Strengths

* Can effectively communicate and mingle with others.

* Can work as a dedicated team member.

* Quick spin up on changing environment.

* Willing to learn and stay abreast of new technology.

* Highly motivated and able to learn and use new CAD tools and

methodologies, creative and productive, able to manage schedule to

deliver projects on time.

I hereby declare that the above written particulars are true to the best of

my knowledge and belief.

BANGALORE NAME: Mahendra kumar MD

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