Senior ASIC Design/Verification Engineer

Hassan Ejaz [pic]

Profile

An all-rounder in front-end digital design/validation, looking for

challenging roles.

Related Experience: 6 Years

Mobile:+601******** Date of Birth: 22/09/1986

Passport:CW1512351

Email:*************@*****.***

Nationality:Pakistan

Employment History

. 10/2010 - Present Snr. Design Engineer

Symmid Corporation Sdn Bhd

Involved in both in house and on site customer projects for Intel,

Altera and

Avago.

. 06/2008 - 10/2010 Asic Design and Verification Engineer

Whizz Silicon Inc

Skill Set

. Micro-Architecture Definition.

. RTL design.

. Proficient in developing Testbench/BFMs (OVM/SystemVerilog).

. Assertions/Functional Coverage.

. Testplan/Testcase development.

. Hands on in both ASIC/FPGA design flow.

. Familiar with low power design concepts, like multiple power domain,

power gating, clock gating, and data retention, UPF definition and NLP

simulations.

. Good knowledge of protocols such as USB2.0/USB3.0, UTMI, PIPE3, PCIe,

JTAG, AMBA AHB/APB/AXI

Career Projects

. eUSB2 PHY (Onsite Intel Project)

eUSB2 is a Next Gen USB2 PHY Responsible for

. Microarchitecture definition, RTL coding, Integration involving

both rtl and bmods for analog blocks.

. Test plan development. Assertions and Testcase addition.

. Developed a repeater BFM.

. Support in SOC debug/Integration.

. Development of UPF for definition of power intent.

. USB2.0 PHY HardIP(Onsite Intel Project)

Responsible for RTL delivery to multiple SOCs using latest Intel

Technology(10,14,21nm)

. RTL development for feature enhancements involving power gating.

. Testcases/Assertions addition.

. Added Powerup and register Programming OVM sequences.

. RTL Bug Fixes and ECOs

. Support in SOC debug/Integration.

. Setup Gate Level Simulation.

. Development of UPF for definition of power intent.

. Configurable IO(Onsite Intel Project)

. Responsible for a testplan for Assertion for blackbox/whitebox

testing.

. EFLASH 72K/256K

. Responsible for RTL and Gate level Simulation.

. Details of work

. Modified existent testcases to cater removal of

MAPRAM.

. Ported the environment from Modelsim to NCSIM.

. Regression runs for RTL/GATE sims.

. CTAG.AMS Hard IP

. Responsible for RTL Design and Verification of CTAG Hard IP

wrapped around PLL IP to provide a DFT solution.

. Details of work

. RTL design of Tap Controller.

. Modified TCB and TPR soft RTL for Hard IP.

. Post synthesis and Post layout sims

. 4 channel LVDS Transmitter(RGB Data)

. Responsible for RTL Design and Verification.

. Details of work

. DDR based RTL design RGB formatter/LVDS interface.

. Build SV Verfication Environment(bfms, scoreboard).

. Polaris, Motor Controller

. Responsible for verification.

. Details of work

. Build System Verilog Environment.

. Added SV Assertion checks.

. Added dynamic performance checks for Cycle, Frequency

and DUTY of AB pulses.

. Added Timing checkers in BFMS.

. Archer, ADC interpolator

. Responsible for verification and FPGA implementation.

. Details of work

. Build Verification Environment.

. RTL/GATE sim.

. Closeloop verification on FPGA.

. Implementation of Spartan 3.

. 8051 micro-controller

. Responsible for verification.

. Details of work

. Added tests for 8051 instruction set in assembly.

. USB3.0/2.0 Host and Device Controller

. Responsible for RTL design and verification and FPGA

implementation.

. Details of work

. RTL design Link Layer.

. Build SV verification Environment(BFMS, Scoreboard).

. Added SV Asserion checks.

. Implementation on Xilinx Vertex5 FPGA

Education

Bachelors in Electrical Engineering 2004-2008

UET Lahore

Tools

. VCS, Modelsim, NCSim

. Lintra

. Modelsim Questa/Zero In CDC

. Spyglass

. LEC Conformal

. Xilinx ISE, Altera Quartus

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