M.Tech VLSI Fresher

Swaroop Darla E-mail: *******.****@*****.***

M.Tech, Microelectronics

Phone No: +91-741*******

Electrical Engineering Department

IIT Bombay

Degree Board Institution Year CPI / %

Post Graduation Indian Institute of Technology,

IIT Bombay 2012 6.80

(M. Tech) Bombay

Under Graduation Andhra University College of

Andhra University 2008 70.13

(B. Tech) Engineering, A.P.

Board of Intermediate

Intermediate/+2 Sri Vani Junior College, A.P. 2004 70.70

Education, A.P.

Board of Secondary

Matriculation PVR M High School, A.P 2002 71.50

Education, A.P.

Objective

Seeking to work in a professional arena that will tap into my skills thereby benefiting the company as well as

giving me a cutting edge advantage over my peers.

Area of Interests

VLSI & CMOS Design, Digital Logic design, ASIC / FPGA Design, RTL Design & Synthesis.

Scholastic Achievements

Achieved All India Rank (AIR)-55 with 99.02% in Graduate Aptitude Test in Engineering (GATE) 2009.

Secured GATE AIR - 401 in pre-final year of under graduation.

Secured First class with Distinction through all semesters in Under graduation B.Tech.

Stood first in mathematics all over the school in matriculation.

Research Project and M Tech Seminar

High Frequency (GHz) Capacitance-Voltage Measurement for Ultra-thin oxide MOS Capacitors

( M.Tech Thesis, Guided by Prof. S.P. Dattagupta)

The project work involves the proper designing of test structure for GHz capacitance measurements and

fabrication of 2.1nm Ultra-thin oxide MOS Capacitors. The device simulations are executed using

Sentaurus tools. The device is characterized using network analyzer. This methodology is effective &

accurate, especially while dealing with the devices having gate dielectric thickness below 2.2nm. This is

applicable to devices those having higher gate leakage currents.

Metal source-drain MOSFET

( M.Tech Seminar, Guided by Prof. Swaroop Ganguly)

Interpreted and summarized literature from various journals and patents on metal source -drain metal

oxide semiconductor (MOS) device which have extremely lower parasitic source/drain resistance and

better immune to latchup problems.

Course Projects & Seminar

Design of a Body-driven Low-Voltage Low-Power two-stage Miller op-amp

To design an Op-Amp with specifications of loop gain: 70db, phase margin: 60deg, with a power

constraint 2µW, 40 KHz unity gain cut-off frequency.

Design of CMOS inverter using process and device simulators

To process a CMOS inverter to meet the specifications of ITRS 2001 Roadmap at 130nm technology and

extracting the spice Level-1, Level-2 parameters from I-V,C-V characteristics.

Others: Effect of interconnect length on delay

Layout of three cascaded minimum sized inverters of TSMC 0.18um technology drawn using MAGIC.

Propagation delay of middle inverter is calculated from extracted netlist. For the 40% increment of that

delay the resultant wire length is estimated.

Seminar : Gate induced Drain Leakage(GIDL) current at high electric fields

Main mechanism and consequences of GIDL and device design considerations for minimizing the GIDL

effect.

Positions of Responsibilities

Led and as a part of 3 members representing the Electrical Department Carrom team which won Silver

medals in institute level PG SPORTS-10.

Coordinated as Teaching assistantship for Solid state devices under Prof. Juzer Vasi(Autumn -10).

Active part in organizing the event of SPIKES-06, a national level student symposium in Andhra Univer-

sity college of Engineering.

Key Extra Curricular Activities & Achievements

Awarded the gold medal for carrom singles in General Championship-2010 which held among all 14

hostels.

W on first prize in Table Tennis for two consecutive years 2007 and 2008 in under graduation.

Winner of carom doubles in Department games in Andhra University.

As a part of winning cricket team in Department games in Andhra University.

As a part of runner-up volley ball team in Department games in Andhra University.

Member of National Cadet Corps (NCC) in schooling.

Areas of Technical Expertise

EDA tools : Xilinx ISE, Mentor Graphics (IC-Studio,DA-IC), Cadence,

NGSpice, Magic.

Hardware Description Languages : Verilog (Modelsim / Isim)

Scripting Language : Perl

Device Simulators : Dios, Dessis

Programming : C, 8085(Assembly)

Operating Systems : W indows & Linux

Engineering Softwares : Latex, MS-Office

M. Tech Courses

Digital VLSI Design, System Design, CMOS Analog VLSI Design, VLSI Technology, Physics of Transistors,

Nanoelectronics, Digital Signal Processing.

Qualities

Flexible and adapt quickly to new working environments .

A good team player with strong interpersonal and communication skills.

Coordinates activities with peers to ensure timely completion.

Enthusiastic and consistently progressed.

Personal Details

Address : Pleasure PG Hostel, Santhinikethan layout, Near SJR Dental College,

Munnekolala Road, Marathahalli, Banglaore - 560037.

Hobbies : Solving Sudoku and some logical puzzles, enjoy cooking.

Languages known : English, Telugu, Hindi.

Date Of Birth : 17-01-1987

Gender : Male.

Marital status : Single.

Contact this candidate