Design Engineering

Udaya Kumar H

# *** **** ******

A M Palya Siragate

Tumkur Karnataka

Email: **********@*****.***

India - 572106

Mobile: +91-962*******

Summary of Qualifications

> Good understanding of the ASIC and FPGA design flow

> Experience in writing RTL models in Verilog HDL and

Testbenches in SystemVerilog

> Very good knowledge in verification methodologies

> Experience in using industry standard EDA tools for the front-end

design and verification

VLSI Domain Skills

HDLs: Verilog and VHDL

HVL: SystemVerilog

Verification Methodologies: Coverage Driven Verification

Assertion Based Verification

TB Methodology: VMM from Synopsys

EDA Tool: Modelsim and ISE

Domain: ASIC/FPGA Design Flow, Digital Design

methodologies

Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Functional

Coverage, Synthesis,

Static Timing Analysis.

Professional Qualification

Pursuing

Master of Technology, Shridevi institute of engineering and Technology,

Tumkur Visveswaraya Technological

University, Karnataka, India

Discipline: VLSI Design and Embedded Systems

Percentage: 70% First Class With Distinction

Year:

June 2015

Bachelor of Engineering, Siddaganga Institute of Technology, Tumkur

Visveswaraya Technological University,

Karnataka, India

Discipline: Telecommunication Engineering

Percentage: 67% First Class

Maven Silicon Certified Advanced VLSI Design and Verification course

From Maven Silicon VLSI Design and Training Center, Bangalore

Extra-Curricular Activities

> Presented Paper titled Texture Feature Extraction of video frames

using GLCM in National level Technical paper presentation at AIT,

Tumkur.

> Attended FEEL Employable Training Programme Stage-I and Stage-II

conducted by CLHRD in SIT.

> Completed Advanced level of the All India General Knowledge

Examination held

During Dec.2003 with First class.

VLSI Projects

Design and Simulation of Wallace Tree multiplier

HDL: Verilog

EDA Tools: Modelsim, Questa - Verification Platform and ISE

> Implemented the Wallace tree multiplier using Verilog HDL

independently.

> Designed Wallace tree multiplier using Verilog.

> Verified the RTL model using Verilog.

> Synthesized the design

GLCM Calculation Based on FPGA System

HDL: Verilog

EDA Tools: Modelsim, Questa -- Verification Platform and ISE

Description: GLCM means Gray Level co-occurrence matrix it is calculated by

directional analysis and GLCM can be used to find second order effects of

vedio frames

> Architected the design and described the functionality using Verilog

HD

> Verified the RTL model using Verilog.

> Generated functional and code coverage for the RTL verification sign-

off

I declare that the information given above is true to the best of my

knowledge.

Date:

Place: Tumkur

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