Design Engineering

Professional Summary:

Skillful, proactive and versatile engineering professional seeking a

challenging full-time position in the areas of Digital Circuit Design and

Verification that would emphasize my knowledge and skill set. Mentors and

peers regard me as team player who can thrive in an entrepreneurial work

environment.

. Proficient in RTL Design using Verilog / VHDL and System Verilog

. Strong Scripting and programming experience using : Perl, Python, Matlab,

C, C++, C#

. Solid hardware engineering background with a concentration in VLSI Design

and Computer Architecture

. Knowledge of ASIC / FPGA Design flow, System verilog verification,

Assertions and Coverage

. Familiarity with DFT techniques like Scan Test, BIST and ATPG

architecture

. Understanding of bus interconnect architecture / protocol : I2C, SPI,

AMBA AXI

. Experience with advance bench test equipment like oscilloscope,

analyzers, multimeters, power supplies

. Good communications skills and ability and desire to work as a team

player

Education:

M.S in Electrical Engineering (GPA: 3.9)

Aug 2014

University of North Texas, Denton, Texas

Thesis: Design space exploration of Domain-Speci?c Recon?gurable

Architectures using Crowd-Sourcing

Coursework: Digital Design and Testing, Analog IC Design, Hardware Design

Methodology for ASIC/ FPGAs, Computer Architecture, Reconfigurable

Computing, Parallel Programming and Analysis, Pattern Recognition

B.Tech in Electronics and Communication Engineering (GPA: 3.6)

May 2011

CVR College of Engineering, JNTUH, India

Skills:

SW Programming: C, C++, C#, .Net, Perl, Tcl, OpenMp, MPI

HW Programming: VHDL, Verilog, System Verilog, Assembly 8086

SW Tools: Visual Studio 10, MySQL, Matlab,

Labview

FPGA/ASIC Tools: Synopsys VCS, Design Compiler, PrimeTime, IC

Compiler

ModelSim, Questa, Cadence Virtuoso,

Encounter, OrCAD PSpice, Xilinx ISE

Lab equipment: Oscillator, Analyzer, Multimeter, Power Supply

Operating Systems: Linux, Unix and Windows(XP, 7, 8)

Work Experience:

Research Assistant: Reconfigurable Computing Lab, University of North Texas

May 2012- Present

. Development and maintenance of scientific puzzle games UNTANGLED &

SmartBricks

. Developed VHDL code generator for reconfigurable array and carried out

power, area simulations using multimedia benchmark suite

. Tools: C#, .Net, SQL Server, SVN, Xilinx ISE, ModelSim, Synopsys Design

Compiler, PrimeTime

Teaching Assistant: University of North Texas

Aug 2012- May 2014

. Courses: Digital IC Design, VLSI Design, Digital Logic Design, Senior

Design Project-VIII

. Taught, Supervised Lab sessions (Demos, Debugging) and revised the Lab

assignments to increase the effectiveness of the lab

Android Developer Trainee, IMobitek, India

Sept 2011 - Nov 2011

. Trained in developing applications using Android SDK

. Designed and tested the Activity Tracer Application in android device

Selected Academic Projects:

Edge-Detection system Design on FPGA using verilog

. Implemented the VGA and SD Card interface for Virtex-5 to read and

display images

. Canny and Sobel Algorithms were used for edge-detection

Design and Verification of Ethernet Switch (Verilog DUT, Systemverilog TB)

. System Verilog Verification Architecture, Constraint Randomization,

Assertions

. Implemented Functional Coverage

Parallel Implementation of K-NN Classifier (C++, MPI, OpenMP)

. Developed a parallel algorithm for K-NN classifier using MPI, OpenMP and

Hybrid OpenMP-MPI

. Estimated the performance, scalability and Iso-Efficiency on AmazonEC2

Cloud Services

SPI 2 I2C Bridge implementation using VHDL

. Understood the concept of SPI and I2C protocols

. Implemented SPI Master and I2C Slave modules to test the design

Computer Architecture Analysis using SimpleScalar (C++)

. Implemented L3 level cache and victim cache to the sim-cache module and

estimated the performance.

. Designed 3bit, Gshare and LGshare branch predictors and estimated their

performance over a range of hardware budget, BHT Sizes (SPEC2000, SPEC95

Benchmark Suit)

MIPS32 Design (5 stage pipeline) on Xilinx Spartan-3E FPGA (Intel Mbedded

Challenge - Finalists)

. Designed and implemented a reduced instruction MIPS 32bit processor using

VHDL

. Instruction and Data Cache are added to the MIPS design

8Bit ALU IC Design (Cadence Virtuoso 0.18um)

. Schematic and Layout were designed for ALU architecture using bottom to

top approach

. Obtained the DRC & LVS Match. Area, Power and Delay were estimated for

the Designed Layout

Selected Publications:

. A. Sistla, K. Patel, G. Mehta, "Crowdsourcing for mapping in design

space exploration of custom reconfigurable architecture designs",

Transactions on Computer Aided Design (Under Review)

. A. Sistla, X. Luo, M. Malladi, R. Marc, G. Raja, G. Mehta, "SmartBricks:

A visual environment to design and explore novel custom domain-

speci?c architectures", Parallel & Distributed Processing, 2014, IEEE

International Symposium, 2014

. A. Sistla, N. Parde, K. Patel, G. Mehta, "Cross-architectural study of

custom recon?gurable devices using crowdsourcing", Parallel &

Distributed Processing, 2013, IEEE International Symposium, 2013

Honors and Activities:

. Recipient of GATS (Graduate Assistant Tuition Scholarship), award for

2012-2013, 2013-2014, UNT

. Recipient of TPEG grant for years 2012-2013, 2013-2014, UNT

. Robocup@IndiaChallenge, Simulation League Champions 2009

. Volunteer tutor at UNT Learning Center

. Member Alpha-Chi Honor Society

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