Inplant Training Engineering

S . Krishnapriya

D/O.S.Sambandam,

***,************ *****,

Chidambaram,

Cuddalore(Dt), E-mail: **********************@*****.***

Pin Code - 608001. Contact No: +91-887*******.

OBJECTIVE:

To obtain a Significant and Challenging position that accelerates me to utilize my Skill and

knowledge effectively for the prosperity of the company.

ACADEMIC PROFILE:

Qualification Institution Board/ University Month Percentage/

&Year CGPA

of

Passin

g

M.Tech Sathyabama University, Sathyabama University, April, 7.94

(VLSI DESIGN) Chennai. Chennai. 2014

B.E Annamalai University, Annamalai University, April, 8.33

(Electronics and Chidambaram. Chidambaram. 2012

Communication

Engineering)

Higher Venus Matric. Venus Matric. May, 69.75

Secondary Higher.Secondary.school, Higher.Secondary.school, 2008

Chidambaram Chidambaram

SSLC Krishnasamy Memorial Krishnasamy Memorial May, 64.90

Matric Higher Matric Higher 2006

Secondary.School Secondary.School,cuddalore,cuddalore

TECHNICAL SKILLS:

Operating Systems : Micro wind 2.1, P-spice, Xilinx, Model-Sim

•

Languages : C,C++,Core VHDL, VERILOG,HDL

•

INPLANT TRAINING:

Bharat Sanchar Nigam Limted

•

Venue: Cuddalore.

Television Broadcasting

•

Venue: Doordarshan Kendra, Puducherry.

RELEVANT SKILLS:

Excellent Advanced Embedded system skills.

•

Excellent Program designing skills.

•

Good Internetworking skills

•

EXTRA CURRICULAR ACTIVITIES:

• Participated in national level technical symposium SURGE-2011 organized by

ANNAMALAI UNIVERSITY, Chidambaram.

• Participated in national conference held on JUNE-2013 conducted by ECE

department,SATHYABAMA UNIVERSITY, Chennai and got first price

• Participated in national conference held on FEBURARY 2014 conducted by ECE

department,Sri VENGADESHWARA COLLEGE, Chennai

M.TECH ACADEMIC PROJECT:

Title : Effective & Efficient Power consumption By Using Multi-Bit Flip-Flops

Description : We proposed to use multi bit flip flop by merging a multi bit flip flop into

a single bit flip flop. The technique will greatly decrease the loading on distribution network

of the clock signal for the multi bit flip flop and thus the overall power consumption. Then,

Experimental results indicate that multi-bit flip-flop is very effective and efficient method in

lower-power designs.

B.E ACADEMIC PROJECT:

Title : An Improved High Speed RS Encoder

Description : we propose RS encoding algorithm according to the method of bit-

parallel multiplication which achieves pipelining on dual basis. On implementing this, the

clock cycle will be reduced to 1clock cycle for single word.

.

PAPER PUBLISHED:

• Paper entitled “A Survey on Post-Placement Techniques of Multibit Flip-Flops ” has

been published in “International Journal of Engineering Research and

Development” e-ISSN: 2278-067X, p-ISSN: 2278-800X, www.ijerd.com Volume 10,

Issue 3 (March 2014), PP.11-18.

• Paper entitled “Design of an area efficient FFT/IFFT processor for WPAN

applications “has been published in “International Journal of Engineering

Research and Development” e-ISSN: 2278-067X, p-ISSN: 2278-800X,

www.ijerd.com Volume 10, Issue 3 (March 2014), PP.06-10 .

• Paper entitled “Effective and Efficient Approach for Power Consumption by Using

Multi-Bit Flip-Flops ” has been accepted for publication in” Coimbatore Institute of

Information Technology “ and attended a National Conference on Advances in

Information and Communication Technology (AICT 2014), 27th & 28th February,

2014 .

STRENGTHS:

• Leadership Quality

• Hard working and has zeal to learn new things.

• Optimistic in nature.

PERSONAL PROFILE:

Name : S.Krishnapriya

Father’s Name : S.Sambandam

Nationality : Indian

Date of birth : October 11, 1990

Language’s Known : Tamil, English.

DECLARATION:

I hereby declare that the information furnished above is true to the best of my

knowledge.

Place:

Date:

KRISHNAPRIYA.S

Contact this candidate