Design Electrical Engineer

NITISH JAIN

**** ********* *****, *** **. **, ********@***.***

Los Angeles, CA - 90007. 213-***-****

Objective

Seeking Full Time (from May 2014) position in the field of ASIC / Digital design / Hardware / Computer Architecture /

Network Processor Design

Education

UNIVERSITY OF SOUTHERN CALIFORNIA, Los Angeles, CA

Master of Science (Electrical Engineering) August 2012 - May 2014

Current GPA: 3.3 / 4.0

Coursework: VLSI System Design (EE577B), Network Processor Design and Programming (EE533), Diagnosis and

Design of Reliable Digital Systems, Digital System Design (EE560), MOS VLSI Circuit Design, Computer System

Architecture, Real Time Computer System

UNIVERSITY OF MUMBAI, Mumbai, India

Bachelor of Engineering (Electronics and Telecommunication Engineering) August 2008 - May 2012

GPA: 72.7/100 (Equivalent GPA: 4.0/4.0)

Coursework: Analog and Digital Communication, Mobile Communication (GSM, CDMA technologies), Digital

Telephony, Electronic and Device Circuits, Communication Networks and Digital Signal Processing

SKILLS

Operating Systems: Windows, Linux

Computer Languages: C, C++, Perl, Tcl, Python

HDL: Verilog, System Verilog (OVM, UVM), VHDL

Engineering Tools: Synopsys IC Compiler, Virtuoso (Cadence), Xilinx ISE, PSOC Creator, Proteus, Labview, NC

Simulator, Tetramax, ModelSim, MATLAB, FPGA, NetFPGA, Deterlab, Matplotlib, OpenGL

PROJECTS

The Alpha Adroit Processor - A Line Speed Network Data Analysis System (Team Leader) April 2014 - May 2014

Design and implementation of a multi core, multi threaded processor coupled with two hardware accelerators for

fast processing of packets, deep packet inspection, and extracting information for data analysis

The interpreted results were displayed on a GUI designed with the help of C++, OpenGL, and a Python script

The Alpha Adroits processor was designed to perform functions such as : 1. Keeping track of malicious activity in

the network; 2. Displaying network topology; 3. Identifying restricted website access if the data exchange between

the nodes exceeds a certain threshold; 4. Identifying a possible distributed attack on a particular server.

For more details please visit the web link: http://www-scf.usc.edu/~adwivedi/page/Alpha_Adroits_team.html

Single Core Processor using custom ISA with Convertible FIFO Memory on NetFPGA Feb 2014 - March 2014

Designed a Custom 5 Stage Processor with ‘32 bit instruction and 64bit data width’ architecture using Schematics,

IP cores and Verilog in Xilinx ISE

Designed and integrated a special FIFO that will allow data to flow between the NetFPGA reference pipeline

designs and your processor. Programmed a translator for Custom ISA assembly code to Binary using C language

Module integrated on a NetFPGA present at ISI DETERLAB and evaluated at a working frequency of 125 MHz

Intrusion Detection System implementation on NetFPGA Jan 2014

Engineered an intrusion detection system which checks for malicious data and drops that particular packet using

packet filtering mechanism. The module was enhanced to support multi -packet recognition and filtering

Built the base module using schematics, IP Cores and Verilog and analyzed possible enhancements for

implementation on NetFPGA.

Memory Read/Write operations and monitoring of Transmission performed via Perl Scripting, optimization of

Design to achieve a high Processing Rate of 125 Mhz

May 2013 – Dec 2013

DDR2 DRAM Memory Controller Design

Designed the Memory controller to perform Scalar and Block Read/Write functions along with Refresh of memory

in time intervals

Performed optimization to reduce critical delay path, allowing it to work at 500 MHz clock frequency in Post

Synthesis using Design Compiler

Oct 2013 – Dec 2013

The FPGA Test System for Arbitrary Logic Functions using C Programming

Designed a Cause-Effect model to store all the faults detected based on their probability of occurrence using a

Ranking Algorithm and a Serial Fault Simulator

Implemented diagnostics tables for real time and potential defects using dynamic Dictionary

Tomasulo Out Of Order Processor July 2013 - Aug 2013

Designed and implemented a 32-bit address, 32-bit data Tomasulo Out of Order Processor with ROB, CFC and

Branch Prediction on the Xilinx Spartan 6 FPGA using Digilient Adept System

It uses Copy Free check-pointing technique with speculative execution

VHDL Programming was used for designing of Re-Order Buffer, Execution Units, Free Register List, Issue Unit,

Branch Prediction Buffer, Store Buffer, Store Address Buffer, Dispatch Unit, Issue Queue, Load Store Queue,

Return Address Stack, Physical Register File and Register Alias Table

CMT Processor June 2013 - July 2013

Designed and implemented a 6 - stage pipelined CMT processor project which supports 4-way Multi

Threading with Non-Blocking Cache and rollback mechanism to deal load with word instructions incurring cache

misses using VHDL

Simulated the designed Rotating Buffer, Thread Scheduler, Store Buffer, Cache Read Miss Status Handling

Register, Cache Write Miss Status Handling Register using Behavioral Simulation

FIFO Implementation May 2013

Designed (in VHDL and Verilog) a single clock FIFO (with N bit pointer, N+1 bit pointer) and a two clock FIFO

using RAM and Block RAMs

General Purpose Multi Cycle CPU March 2013 - April 2013

Design and implementation of a general purpose Multi -cycle CPU which can support general memory transfer and

arithmetic instructions in Cadence (both schematic and layout) with focus on optimization of area*power*delay

product with a 64*16 SRAM acting as the ultimate source to store data

Instruction Fetch and Decode stages were implemented in software using Perl which converts the given

benchmark program to Cadence input vector files and also carries out automated result verification.

Real Time Operating System implementation using Microcontroller ATmega128 Feb 2013 - April 2013

Programmed a Snake game using Embedded C and other components from the board using an peripheral

interconnect

Learned various functions which could be implemented on this Microcontroller ATmega128 like GPIO:

Reading/writing into Ports, LED programming, LCD programming, ADC Programming, Joystick Interface,

USART programming, Timers/Interrupts, EEPROM Reading and Writing

Jan 2013 – May 2013

Out-of-Order Superscalar Processor

Design of an out-of-order superscalar processor within the given area budget to achieve the best performance

(MIPS being the metric) for a given set of benchmark programs.

Aug 2012 – Dec 2012

MPSoC Data Transmission Router using Bitonic Sorting Network

Designed and implemented an MPSoC Data Transmission Router to achieve resource allocation based on the

priorities of the four data transmitters in Cadence optimizing the area*clock frequency product

Aug 2012 – Dec 2012

Computer Organization-MIPS Pipeline Design

Designed and verified a 5 - stage in-order linear instruction pipeline with early branch implementation based on

MIPS ISA incorporating hazard detection, stalling, forwarding and flushing mechanisms in Verilog.

Undergraduate Research (Team Leader) July 2011 - May 2012

Adviser: Dr. Sanjeev Ghosh (Deputy HOD, and Associate Professor, TCET)

Implemented "IMAGE ENCRYPTION USING DIGITAL SIGNATURE" Using Image Processing in Matlab.

SHA-256 was used for image encryption onto which the extracted hash was digitally watermarked at the sender’s

side. On the receiver’s side we extracted the data from the watermarked image and then again applied SHA -256 on

the image to generate the hash verified it with the extracted hash to check for authenticity of transmitted data

I was to generate SHA-256 encrypted data and to create a GUI in Matlab for project presentation

Miscellaneous Projects

Maze Router Algorithm implementation using Verilog

Automation of simulation process and perform result checking to generate a testing report using Python

Familiarized with Code Coverage, clock gating, Time Stealing and multicycle timing concepts(VHDL)

AWARDS

Recipient of the JRD Tata Scholarship for securing an aggregate of above 75 in one academic year

Recipient of the Certificate of Merit completion of C, C++ courses held at NIIT

EXTRACIRICULLAR ACTIVITIES

Director of Finance in Association of Indian Students @ USC

Board member of International Student Assembly @ USC

Technical Head IEEE @ Thakur College of Engineering and Technology and Organizer of various cultural events

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