Fpga Design And Verfication Engineer

Curriculum Vitae

B.MAHENDRANATH REDDY Email_id: ************@*****.***

D/o :4/369-Upstairs,Geethaashram Street,

Mobile Number: 817-***-****

Proddatur,YSR District, A.P

Career Objective:

Fully qualified VLSI Verification Engineer with over 1.7 years experience.

Currently seeking employment in VLSI Design and Verification (automotive

preferred) as Designer / Developer / Verification Engineer . I would welcome

the opportunity to make use of my knowledge to work in a challenging and

growth oriented industry with very motivated people.

Core Competency:

Good understanding of fundamentals of Transistors and circuit theory

Comprehensive knowledge of the methodologies and applications of advanced

verification tools

Good knowledge of Verilog RTL coding and Digitial Design Concepts and FSM

Design.

Good knowledge in verification methodologies and Testbenches in System

Verilog.

Experience in EDATools like Xilinx Ise DesignSuite, Matlab, Modelsim, Altera

Quartus II.

Good Knowledge in Perl Scripting and Shell Scripting for Tools.

Experience in working Xilinx System Generator and Chipscope Pro and PlanAhead

Tool.

Experience:

1Year 3Months Worked FPGA Designer and Verification Engineer in Nano

Scientific Research Centre Pvt. Ltd Hyderabad from March 2013 to May 2014.

Four Months Worked as VLSI Intern in Maven Silicon Soft Pvt . Ltd at

Bangalore from Nov 2012 to Feb 2013 .

Five Months Worked as VLSI Trainee in Maven Silicon Soft Pvt. Ltd at

Bangalore from June 2012 to Oct 2012.

Academic Qualification :

> Completed Master of Technology on " VLSI SYSTEM DESIGN" with 82.3%

under JNTU Anantapur University A.P.

> Completed Bachelor of Technology on " Electronics & Communication

Engineering " with 75.14 % under JNTU Anantapur University A.P.

> Done a Course on " Advance VLSI Design and Verification" from Maven

Silicon Soft Pvt . Ltd at Bangalore From Period of June 2012 to Oct

2012.

Extra-curricular Activities:

> Attend the course "Teaching Engineering using LabVIEW " at Sri

Venkateswara college of Engineering & Technology.

> Attend a national level workshop on "VLSI & Image Processing" at Sri

Venkateswara college of Engineering & Technology.

> Participated in a National conference at NHCE Bangalore on " Recent

Advances in Electronics & communication Engineering".

Technical Skills:

HDLs :Verilog and VHDL.

HVL : SystemVerilog

Verification Methodologies :Coverage Driven Verification,Assertion Based

Verification.

TB Methodology : OVM, UVM.

EDA Tool :Modelsim, XilinxISE Design suite, Questasim,

Altera Quartus II .

Active - HDL, Matlab.

Back End Tool : Tanner Eda, HSpice, LTSpice, MicroWind Lite.

Scripting Language :Shell Script, Perl-Script, Basic Tcl Script.

Software Language :C and C++.

Domain : ASIC/FPGA Design Flow, Digital Design

methodologies.

Knowledge :RTL Coding, FSM based design, Simulation, CMOS

concepts,

Code Coverage, Functional

Coverage, Synthesis,

Protocol Knowledge :MGC-ICPIT, FIFO, GPIO, UART, RS232, SPI, I2C.

Operating System : Windows Xp, Windows7, Ubuntu.

VLSI Design Project :

M.Tech Project: High -Speed and Low - Power Viterbi Decoder Design For TCM

decoder

Using 2 - Step Pre-computational architecture.

Description : In this project, Viterbi decoder is design for TCM

Decoders with code rate . Basically Viterbi Decoder is Dominant module

for power dissipation,for that purpose only to reduce Power, a newly two

step pre -computational architecture which act as Threshold unit for low

power designs. Implemented Module are Convolutional Encoder with Code rate

and Constraint Length -7, Branch Metric Unit, Add-Compare Select unit,

Surviour Metric Unit, Path Metric Unit, Threshold Generator Unit, Purge

Unit.

Language and Tools : Verilog, Shell Script MakeFile, Xilinx ISE Design

Suite, Modelsim,

Xilinx Power Analyzer.

Project : Implementation OFDM (Orthogonal Frequency Division Multiplexing)

for

Software Defined Radio.

Description : A Software Defined Radio (SDR) is a transmitter and receiver

system that uses digital signal processing (DSP) for coding, decoding,

modulating, and demodulating data. The Implemented Modules are Quadrature

Phase Shift Keying (QPSK), Fast Fourier Transform (FFT) Algorithms and most

importantly, the algorithm for Direct Digital Frequency Synthesis (DDFS)

for both transmitter and receiver . A digital frequency synthesizer with

optimized time and area resources has been proposed for the SDR. This VLSI

implementation of the DDFS computes the sine and cosine function on a

single edge of clock, thus proving to be optimized in terms of area and

speed.

Language and Tools Used : Xilinx ISE Design Suite, Modelsim, Verilog.

Project : Efficient Majority Logic Fault Detection in Euclidean Geometry

Low Density

Parity Check and Difference Set Codes.

Description: Error-detection method for difference-set cyclic codes and

Euclidean Geometry Low Density Parity Check with majority logic decoding

. Majority logic decidable codes are suitable for memory applications due

to their capability to correct a large number of errors. The proposed fault-

detection method signi?cantly reduces memory access time when there is no

error in the data read. The technique uses the majority logic decoder

itself to detect failures, which makes the area overhead minimal and keeps

the extra power consumption low. Implemented Code rate for EG- LDPCS (63,

37), and DSC- codes (73, 45) codes are implemented.

Language and Tools Used : Xilinx ISE Design Suite, Modelsim, Verilog.

Project : Product Codes For Error Correction Using Reed Solomon & Hamming

codes.

Description : In this paper use of product code based schemes to support

higher error correction capability product codes which use Reed-Solomon

(RS) codes along rows and Hamming codes along Columns and have reduced

hardware overhead. when the numbers of errors due to increased

program/erase cycles increases. Implemented Modules are Reed Solomon Codes

(255, 247), Hamming Code is (72, 64) are used and developed.

Language and Tools used : Verilog, XilinX ISE Design Suite and Modelsim.

Project : Data Encoding Schemes in Networks on Chip using Worm Hole

Routing.

Description : Data encoding techniques as a viable way to reduce both power

dissipation and energy consumption of NoC links. The proposed encoding

scheme exploits the wormhole switching techniques and works on an end-to-

end basis. That is, ?its are encoded by the network interface (NI) before

they are injected in the network and are decoded by the destination NI.

Language and Tools Used : Xilinx ISE Design Suite, Modelsim, Verilog.

VLSI Verification Projects:

Project : UART Verification using OVM Methodology

Description : UART is a type of "asynchronous receiver/transmitter", a

piece of computer hardware that translates data

between parallel and serial forms. The "universal" designation indicates

that the data format and transmission speeds are configurable. A UART is

usually an individual (or part of an) integrated circuit used for serial

communications over a computer or peripheral device serial port. UARTs are

now commonly included in microcontrollers. A dual UART, or DUART, combines

two UARTs into a single chip.

Language and Tools Used : Xilinx ISE Design Suite, Modelsim, Verilog.

Project : MGCICIPIT Verification using OVM Methodology.

Description : The ICPIT provides a basic interrupt controller functionality

together with the capability to implement two timers which can also be

configured to generate interrupt. There are two timers available, one is

intended as a programmable interval timer and the other as a watchdog

timer. In the PIT count register and count down .when it reach,it produce

a time_out pluse, which is one cycle wide and reload the count register

value on the next clock edge.

Language and Tools Used :, Modelsim, Verilog, Sytem Verilog, Shell

Script.

Project : SDRAM Controller Verification using UVM Methodology

Description : Synchronous DRAM has become a Main Stream Memory of Choice in

embedded System Memory design. For high - end applications using Processors

the interface to the SDRAM is Supported by the processor 's built in

peripheral Module. The Synchronous interface and fully Pipelined internal

architecture of SDRAM allows extermely fast Data rates is used efficiently.

The SDRAM Memory Bank is addressed by row and column

Language and Tools Used :, Questasim, Verilog, Sytem Verilog, Shell

Script.

Project : SPDIF Receiver Verification using UVM Methodology

Description : The Sony/Philips Digital Interconnect Format (S/ PDIF) core

is a digital audio interface controller that implements the International

Electronic Commission (IEC) 60958-3 interface for transmitting and

receiving audio data. It can be used in a receive or transmit mode and

delivers or accepts audio data from an AXI4-Stream input. The S/PDIF core

is designed for use in audio systems, and is used with the LogiCORE IP

Display Port core for audio data transfers.

Language and Tools Used :, Questasim, Verilog, System Verilog, Shell

Script.

HardWare Co- Simulation Projects:

B. Tech Project: The Impercepitlibie Video Watermarking Based On The Model

Of

Entropy.

Description : The video watermarking used for digital copy right

protections. In this we are using the concepts of model of entropy to

acquire the motion of the information. In this DWT (Discrete Wavelet

Transform) transformation is used for to embedded the watermarklog at the

respective sideband. In this Project we divided the video into number of

Frames and acquire the Motion of Informations and By using DWT

Transformation we embed the log at Low hand Side and combine the all the

Frames.

Language and Tools : Matlab2007, C Language and Matlab Simulink Model.

Project: Design of FIR Filter using Simulink and System Generator

Configure Matlab.

Description : A FIR filter is designed by finding the coefficients and

filter order that meet certain specifications, which can be in the time-

domain (e.g. a matched filter) and/or the frequency domain (most common).

Matched filters perform a cross-correlation between the input signal and a

known pulse-shape. The FIR convolution is a cross-correlation between the

input signal and a time-reversed copy of the impulse-response. Therefore,

the matched-filter's impulse response is "designed" by sampling the known

pulse-shape and using those samples in reverse order as the coefficients of

the filter.

Language and Tools : Xilinx ISE, Matlab HDL Coder, Matlab FDA Tool.

Personal Details:

Father's Name : B. Nagi Reddy

Date of Birth : 10-03-1989.

Gender : Male

Nationality : Indian.

Languages Known : English, Telugu, Hindi

Hobbies : Listening Music, Movies.

Declaration: I hereby declare that above information is true and written

with best of my Knowledge and beliefs.

Contact this candidate