Design System

CURRICULUM VITAE

MANOJ T R

Email: *********@*****.***

Final year Postgraduate student

VLSI Design and Embedded system & B.E (ECE)

phone: +91-984*******

VTU

Objective: I aspire for a creative & challenging work where I can enhance

my technical and interpersonal skills, thereby giving me an opportunity to

expand my knowledge and gaining valuable professional experience.

Area of Interest: VLSI, Digital Design, VLSI Design Verification,

Microprocessor Architecture, Data Communication, Embedded System.

Educational Qualification:

DEGREE UNIVERSITY YEAROF PASSING PERCENTAGE

M.Tech (VLSI Design CMRIT, 2014 73.0(till 3rd sem )

and Embedded Bangalore

System)

B.E.(ECE) KIT, 2011 63.10

Tiptur

12th (PUC) PU Board 2007 75.76

Karnataka

10th (SSLC) KARNATAKA STATE 2005 81.82

BOARD

Technical/ Software skills

Programming Languages C, C++, Verilog, VHDL, 8086 Assembly Level

Programming.

Tools MATLAB, CADENCE, Xilinx, Keil.

Operating System Windows, Vista, Linux.

Projects Done:

. Zig-bee sensor network using arm7 processor

My project is based on wireless sensor networking to control and

monitor different devices according to the sensor parameters attached

to it. We use Zigbee protocol to make effective, error free,

convenient network. Hopefully it would make life more convenient,

environmentally friendly and safe.

. On-Chip Systolic Networks for Real-Time Tracking of Pair-wise

Correlations Between Neurons in a Large-Scale Network

The correlation map of neurons emerges as an important

-mathematical framework for a spectrum of applications including

neural circuit modeling, neurologic disease bio-marking and neuro

imaging. However, constructing a correlation map is computationally

expensive, especially when the number of neurons is large. This paper

proposes a hardware design using hierarchical systolic arrays to

calculate pair-wise correlations between neurons.

Important Courses Done

. Analog and Digital VLSI Design (ADVD)

. Analog Electronics

. Embedded system

. System on chip

. Microprocessor Programming and Architecture

. Digital system design using Verilog.

PERSONAL DETAILS

Name : MANOJ T R

Date of birth : 21/081990

Sex : Male

Nationality : Indian

Address : S/O RANGE GOWDA T

Thuruganahalli, aluru taluk

Hassan-572218.

DECLARATION

I hereby agree that the above information's are true to the best of my

knowledge and belief

Place: Bangalore

(MANOJ T R)

Date:

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