Project High School

RESUME

DHAVALKUMAR HARESHKUMAR PADIA

***,"SLV Grand",

Email ID: **********@*****.***

19th main 36th Cross,

Mobile: +91-809*******

1st Stage 5th Block

HBR Layout,

Bangalore-560043,Karnataka.

Objective

Seeking a challenging technically positioned Job in Verification sector,

that provides a highly motivated, progressive, friendly environment, which

allows me to pursue my career and expand my knowledge and skills.

Internship (LSI Corporation Bangalore)

Project Name : Implementing Register Abstraction Layer (RAL)

tests, verification of debug logic and other

automation for Memory Subsystem (MSS) verification.

Duration : 9 months

Description : To verify the access type of the register in EDS and RTL

are same and whether the read and write operations work fine. Also

verify the reset value of each registers match and to check the decode

region of registers.

Responsibilities :

Was involved in preparing and execution of the test cases for performing

read/write and reset value check for all pre-verified and non-preverified

IP's register using UVM for RAL Models.

Prepared & executed tests for performing read/write for all preverified

IP's using OVM.

Used Questa tool for doing profiling of the tests.

Technical Skills

HDL : Verilog

HVL : SystemVerilog

Methodology : UVM

Scripting : PERL,C

Protocol : AMBA AXI

Tools : VCS

Academic Project

Project Name : An Implementation of the architecture of software defined

cognitive radio"

Description : The architecture of a software defined cognitive radio is

realized which caters to the specific base band processing

requirements in the changing environment. An OFDM based radio

physical layer containing 64 bit FFT/IFFT block, modulator and

a cor-relator.

A 4th semester project,done at MCIS, Manipal.

Project Name : Efficient Design and FPGA Implementation of JPEG Encoder

using Verilog HDL.

Description : The JPEG encoder is a major component in JPEG standard

which is used in image compression. It involves a complex sub-

block discrete cosine transform (DCT), along with other

quantization, zigzag and Entropy coding blocks.

A 3rd semester mini project, done at MCIS,Manipal.

Project Name : Microcontroller based Fiber Optic Communication System

Description : It is a simplex way of communication in which the data or

information is transmitted through the pulse of

light i.e. through an Optical Fiber cable. In this project

music, temperature, humidity and string of characters (ASCII)

are given as four separate inputs. At the receiver the photo

detector is used to convert the light into digital data. From

this project we can conclude that by using Fiber optic cable no

data is lost during the transmission.

This project during our last year means during

the 7th & 8th Semester of BE.

Educational qualification

Class/Course Name of Institute Board/University Year of Marks%

Passing

Master Of Science Manipal Centre Manipal Academy of Pursuin 3rd Sem &

for Information Higher Education g 4th Sem GPA

And Technology Science (MAHE), Manipal

( VLSI Design) 8.20

BE Valia Institute Veer Narmad South 2011 65.77 %

(Electronics & of Technology, Gujarat University,

Communication) Valia Surat

HSC Shree P V Modi GSHSEB 2007 62.60 %

High School,

Rajkot.

SSC Saint Francis GSEB 2005 74.00 %

School, Jetpur.

Areas of field interest

RTL Verification & Design

Seminars

. Radio Frequency Identification & Detection (RFID).

. Hardware Trojan.

. Parallelization in Video Encoding.

Hobbies

Traveling, Music, Reading and Dancing.

personal profile

Father's Name : Hareshkumar Dhirajlal Padia

Date of Birth : 27-12-1989

Sex

: Male

Languages Known : English,

Hindi and Gujarati

Nationality : Indian.

Permanent Address : "Manibhuvan"

Shankdi Street,

Mota Chowk,

Jetpur-360370

Rajkot, Gujarat

Declaration

I hereby declare that the information furnished above is true to the best

of my knowledge.

Place:

Date: DHAVALKUMAR HARESHKUMAR PADIA

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