Design Engineer
Resume:
AYUSH SOOD
Mobile: +919********* E-Mail: *****.******@*****.***
Analog, Digital & Mixed Signal IC Design Engineer
SYNOPSIS
Seeking Job Opportunity with following technical & behaviour skills
Cadence – Virtuoso, Spectre and Mentor Graphics EDA tools. Modelsim 6.5, HSPICE and
Xilinx’s Project Navigator
Circuit design (transistor and system level) and layout in submicron CMOS (45nm)VHDL,
Verilog HDL
C++, MS Office, MATLAB, Basics of networking involving network and server setups.
Operating System-Windows Family, Linux and Mac OSX
I am an effective communicator with good relationship building & interpersonal skills. Strong
analytical, problem solving & organizational abilities. I am a team player and go getter by nature. I
am a result oriented individual with ability to deliver work in given time
EDUCATION
MS Electrical Engineering (VLSI) from Arizona State University, Tempe, Arizona, USA, March
2014
Electronics & Communication Engineering from SRM University, May 2012
EXPERIENCE & PROJECTS UNDERTAKEN
Design Engineering Intern at Indian Institute of Technology (IIT), Bombay
May’13 – August’13
OTA Architecture implementation for R.R. Harrison and C. Charles, "A low-power low-
noise CMOS amplifier for neural recording applications," IEEE Journal of Solid-State
Circuits, 38: 958-965, June 2003 – Design, simulation and analysis of various OTA
architecture for biomedical applications at 180nm CMOS process.
PROJECTS UNDERTAKEN– Have worked on following projects during course of my studies and internship -
Amplifier Design, A/D converter Design, LDO Design, Standard Cell Layout, Timing Analysis, Switch Capacitor Filter
Design
Single ended PMOS input folded cascode amplifier – Transistor level design and
simulation of a PMOS input folded cascode amplifier with Class AB buffer output stage.
Modelling and simulation of a 12 bit, 80 MHz pipelined ADC – Design and simulation of
a spectre macro model of a differential RSD based pipelined ADC
Low Dropout Regulator (LDO) – Design, simulation and analysis of a LDO at 0.25 micron
CMOS process that regulated the output voltage at 1.5V.
Custom design of 16 Bit Kogge – Stone Adder – Design and simulation of a lego based
hard IP design of 16 bit Kogge – Stone Adder on 45nm PDK
8 bit even Parity Generator – Design and layout of 8 bit even Parity Generator that
minimized Energy Delay Product (EDP) and total layout area.
Switch Capacitor Filter Design – Design of band pass filter followed by a notch filter for a
cordless phone IC application.
Buck – Boost Converter Design – Design of Buck, Boost converter, inverter and a PFC for
a SMPS application
Traffic Light Controller – Programming and simulation of Traffic Light Controller using
VHDL (Verification using Verilog) and simulation on XILINX FPGA kit, under guidance of Mr.
Naresh Dobal (CETPA InfoTech Ltd.)
PERSONAL INFORMATION
a. Date of Birth :05 December 1990
b. Current City: Noida (U.P)
c. Native Place – H.P
I am Tall, Well built, Unmarried, Willing to relocate for job, willing to travel for assignments and
available to join at short notice. Information given above is true to best of my knowledge,
References can be made available
June 2014 Ayush Sood
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