c,vhdl,device design
Resume:
SHRUTIKA SATYANARAYANA
E-mail: acepdx@r.postjobfree.com, Contact No: 991-***-****
Address: Type 5/5-B University of Delhi, South campus, New Delhi 110021
EDUCATION
Expected Graduation: May 2014
Thapar University, Punjab, India
CGPA: 8.65
Master of Technology (VLSI design)
Graduation: June 2011
Bharati Vidyapeeth University, Maharashtra, India
Percentage: 65.2% (Distinction)
Bachelor of Technology (Electronics Engineering)
TECHNICAL SKILLS
Languages: C, VHDL, 8051 and Arm microcontroller.
Softwares and Tools: MATLAB, Xilinx ISE, Capture(Mentor Graphics), Model Sim (Mentor Graphics), Keil, Vis
TCAD(Cogenda), Atlas(Silvacco)
PROJECTS
Modeling of Gate Leakage Current Through Ultrathin Gate Oxides and March 2013 to Present
High-K/Sio2 Gate stacks in Double Gate Fully Depleted SOI MOSFET:
Designing a low power Double Gate Fully Depleted SOI MOSFET using
Visual TCAD tool.
Modeling the Direct tunneling current through ultrathin gate oxides and
High-k/sio2 gate stacks.
Least Loaded Routing Algorithm: July 2010 to May 2011
Designed an algorithm to create Least Loaded Routing Protocol using the
communication toolbox of MATLAB.
This algorithm allowed the data packet to follow the least congested path.
Stepper Motor Control System: July to November 2009
Designed and created a stepper motor control system based on AT89C51
microcontroller to control the rotation of a DC stepper motor in clockwise
and anti-clockwise directions.
TRAINING
Bharat Sanchar Nigam Limited (BSNL),Chinchwad, Pune January to February 2011
Attended a six-weeks training programme based on GSM and GPRS
networks, Power Plant, CDOT and broadband operations.
ACTIVITIES
Facilitate study lessons to underprivileged children as a member of college August 2012 to present
club-Lakshya.
Organized robotics workshops and mock placement events as treasurer of Concepts. January to July 2010
Developed marketing and publicity strategies during the annual college festival -Bhartiyam. October 2010
Contact this candidate