Iyer Suraj Ramaswamy

Email: aceork@r.postjobfree.com

Contact: 811*******/ 902-***-****

OBJECTIVE

To contribute and improve my knowledge and skills as an RTL design/verification intern.

PROJECTS UNDERTAKEN

• Design of reconfigurable 2-D LFSR for BIST in System-On-Chips (Jan 2014 –May 2014)

Studied in detail the working of LFSRs, 2-D LFSRs to design a reconfigurable version that uses same

hardware to produce different deterministic ordered test patterns which could be used to test various

blocks in an SOC.

• Multiplier using UCSLA adder (Jan 2014 - May 2014)

Design of an 8-bit, 16-bit and 32-bit multiplier using Uniform Carry Select Adder in Verilog HDL.

Synthesis using various low power and DFT constraints, Physical Design were completed within the

stipulated time.

• FPGA Based Object Tracking Algorithm Implementation (July 2013 – Nov 2013)

Object Tracking was achieved using Background Subtraction Technique. Parallelism in hardware was

achieved by splitting the 80 x 80 image into 12 parts of 20 x 20 each. Simulation performed

successfully on MATLAB.

• FPGA implementation of an enhanced processor (July 2013- Nov 2013)

Design of a 16 bit processor in Verilog HDL. Synthesis done in Quartus Altera. Successfully

implemented on Altera DE1 EP2C20F484C7 Board.

• A Fair Fare System (Final Year B.E project 2011-2012 )

A digital Fare Meter was designed to detect tampering in the meter. Could be connected with a Java

application in the customers’ mobile phone via Bluetooth which calculates fair independently. Learnt

Basic Bluetooth Protocols, Embedded C programming. Used microprocessor Atmel 89S52 to build a

digital meter with 3 levels of tampering incorporated within. IR module was used to count number of

rotations of the wheel. Bluetooth module was used to transmit count to a Java application in user’s

mobile phone.

TECHNICAL SKILLS

• Operating Systems: Linux, Windows XP, Windows 7, Windows 8.

• Programming Languages: C++, Java, MATLAB.

• HDL: Verilog HDL.

• Scripting Languages: Perl, TCL.

• Softwares used: Circuit Design – Cadence Virtuoso.

Pre Layout simulation – Modelsim Altera, Cadence NC-SIM.

Synthesis – Quartus Altera for FPGA, Cadence RC.

Physical Design – Cadence Encounter.

PERSONAL SKILLS

Strong coding skills, Self motivated, Enthusiastic about learning new skills, Quick learner,

Comprehensive problem solving ability, Creative, Artistic, Team oriented, Punctual.

EDUCATIONAL CREDENTIALS

• M. Tech VLSI DESIGN Sem 2, JAN 2014 – MAY 2014

VIT University

GPA - 8.22

CGPA – 8.21

• B.E Electronics and Telecommunication, JUNE 2008 - MAY 2012

S S Jondhale College Of Engineering, Mumbai University

Agg. Percentage: 55.6%

• HSC- Maharashtra State Board, MAY 2008

Birla College of Science, Kalyan

Percentage: 60%

• SSC- Maharashtra State Board, MAY 2006

St. Therese Convent High School, Dombivli

Percentage: 87.60%

PROFESSIONAL CERTIFICATION

Web Component Development using Java Technologies by NIIT, December 2012

PERSONAL DETAILS

D.O.B: 31/01/1991

Languages known: English, Hindi, Marathi, Tamil, Malayalam, German.

Hobbies: Solving Puzzles, Sketching, Origami, Table tennis.

Contact Address: 1403, Tower 4, Soham Park,

Hari Om Nagar, Mulund E – 400081

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