Masters in VLSI

VINOD KUMAR J

(Email: ***************@*****.*** / Mob: +91-988*******)

Career Objective:

To enhance my professional skills to keep up with the cutting edge of

technologies and obtain a long term career.

Qualifications:

. M.S (VLSI CAD):- from MCIS Manipal, affiliated to Manipal University,

Karnataka with the percentile of 7.99/10 (2013).

. B.E - ECE:- from SJCIT, Chikkaballapur, affiliated to Visvesvaraya

Technological University, Karnataka with an aggregate of 57.21%

(2011).

. Intermediate:- from St.Aloysius PU College, Bangalore, affiliated to

Karnataka PUE board, Karnataka with an aggregate of 47.60% (2006).

. SSLC:- from Maria Niketan High School, Bangalore, affiliated to KSEEB,

Karnataka with an aggregate of 74.24% (2004).

Technical Skills:

Electronic Design Packages : Xilinx ISE Design Suite, Model sim, Design

Compiler,

Magic, VCS, Questa Sim.

Programming Languages : Verilog, C, System Verilog, Verification

using UVM

and OVM, PERL scripting, basic in C++, Hspice,

Bspice.

FPGA Boards : Xilinx FPGA Spartan 3E, Virtex 5,

Altera Cyclone II.

Familiar Protocols : Router, Serial peripheral interface.

Familiar OS : Microsoft Windows, Linux.

Applications : Microsoft office Suite (Word, PowerPoint).

.

VLSI Domain courses undertaken:

Maven Silicon Certified Advanced VLSI Design and Verification course

from Maven Silicon Softech Pvt Ltd., VLSI Design and Training Center,

Bangalore. Year: 2014

Experience:

. Worked as an Intern in BCS Innovations, Bangalore (01/08/12 to

25/07/13).

Project Expertise:

1) Title: Router 1x3 - RTL design and Verification

HDL : Verilog

HVL : UVM

EDA Tools : Modelsim & ISE

Description: The router accepts data packets on a single 8-bit port

called data and routes

the packets to one of the three output channels, channel0, channel1 and

channel2.

. Architected the design and described the functionality using Verilog

HDL.

. Architected the class based verification environment using system

Verilog

. Verified the RTL model using SystemVerilog.

. Generated functional and code coverage for the RTL verification sign-

off

. Synthesized the design.

3 SPI Controller Core - Verification

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Questasim

Description: The SPI IP core provides serial communication capabilities

with external device of variable length of transfer word. This core can be

configured to connect with 32 slaves.

Responsibilities:

> Architected the class based verification environment in UVM

> Verified the RTL module using System Verilog

> Generated functional and code coverage for the RTL verification sign-

off

2) Title : A Low Power VLSI Architecture for Image Compression using DCT &

IDCT

Image compression is an important topic in digital world. Here I

am implementing the low power VLSI architecture for image compression

system using DCT and IDCT. Discrete Cosine Transform (DCT) is the most

widely used technique for image compression of JPEG images and is a lossy

compression method. The architecture of DCT is based on Lo-effler method

which is a fast and low complexity algorithm. In the proposed architecture

of DCT multipliers are replaced with adders and shifters. Low power

approaches like Canonic signed digit representation for constant

coefficients and sub-expression elimination methods have been used. The 2D

DCT is performed on 8x8 image matrix using two 1D DCT blocks and a

transposition block. Similar to DCT, the IDCT is also implemented using the

Lo-effler algorithm for IDCT. Verilog HDL is used to implement the design.

ISIM of XILINX is used for the simulation of the design.

Role & Challenges : Understanding the concept of DCT & IDCT, RTL

coding and

FPGA implementation (Spartan 3E).

Personal Details:

Name : Vinod Kumar J

Father's Name : L V Jayaram Reddy

Gender : Male

Date of Birth : 18 January 1989

Nationality : Indian

Marital Status : Single

Hobbies : playing cricket, listening to music, reading novels.

Languages known : Kannada, English, Telugu, Tamil & Hindi

Permanent Address :

#2/35 V.S.T Road, Lingarajpura

St.Thomas town post,

Bangalore-560084

Declaration:

I hereby declare that above information is true and written with

best of my

knowledge and belief.

Date:

Place: (Vinod

Kumar J)

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