G VISHNUVARDHAN YADAV

Email id: aceofa@r.postjobfree.com

Mobile Number: 888-***-****

Career Objective:

Seeking for the position as a Design & Verification Engineer that enables me to utilize my skills

for a positive contribution to the organization.

Core Competency:

Good knowledge of Digital Design Concepts

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Good knowledge of Verilog RTL coding.

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Good working knowledge of Linux.

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Good knowledge of System Verilog.

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Good knowledge in UVM methodology for Verification.

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Good knowledge in ASIC Design Flow.

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Hands on experience on Industrial tool like QuestaSim.

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Good exposure to technology by undergoing additional training in VLSI.

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Implemented a VLSI project during my undergrad.

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Basic knowledge of C programming.

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Basic knowledge of Static Timing Analysis (STA).

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Education :

Institute Year of

Degree Discipline Aggregate

University Passing

RV-VLSI Design

PG Diploma VLSI 2014

Center

Rajeev Gandhi

College of

Electronics &

BE/B.Tech Engineering and 2013 71 %

Communication

Technology

JNTU

Govt Institute of

Electronics &

Diploma/Polytechnic Electronics 2009 72.8 %

Instrumentation

SBTET

Sri Navanandhi

10th SSC HighSchool 2004 72.5 %

SSC

Academic Projects:

Pipelined C2MOS Register High Speed Modified Booth

Title:

Multiplier

Role: Designing & Simulation

Rajeev Gandhi Memorial College of Engineering and

Organization:

Technology, Nandyal

Duration of Project in Months: 3

Description: main project Pipelined C2MOS Register High Speed Modified

Booth Multiplier, aims at increasing the speed of signed and

unsigned multiplication by using pipeline concept in Modified

Booth Multiplier, which has been useful in DSP(Digital Signal

Processing) applications

Tools Used : Tanner EDA, Tspice, Hspice

Title: VERIFICAION OF FIFO

Role: Verifying Design

Organization: RV-VLSI

Duration of Project in Weeks: 3

Description: Aims at Developed Test bench architecture and verifying the

design as bug free by using Verilog, System Verilog &

Universal Verification Methodology (UVM).

Tools Used : QuestaSIM and text editor (gedit).

Deliverable/Challenges Faced: 1)to check all the corner cases possible for the proper

functionality of FIFO.

Title: DESIGNING OF VEDIC MULTIPLTIER

Role: Designing & Verification

Organization: RV-VLSI

Duration of Project in Months: 1

Description: Improves the speed of multiplication from the normal shift and

adding process. Designed &verified 2bit Vedic multiplier in

Verilog and replicated it to 4bit followed by 8bit. Verified the

entire design by writing a full self-testing test bench for all the

corner case

Tools Used : Questa SIM and a text editor (gedit)

Title: VERIFICATION OF UART USING UVM

Role: Verifying Design

Organization: RV-VLSI

Duration of Project in Weeks: 2

Description: The design under verification is fully functional, synthesizable

universal asynchronous receiver transmitter soft core with

microprocessor bus, ideal for embedded processor applications

or system-on-programmable-chip. Verified it by writing test

cases after forming UVM verification architecture using system

verilog.

Tools Used : Questa SIM and a text editor (gedit).

VERIFICATION OF SUBSYSTEM WITH

Title:

COMMUNICATION INTERFACE

Role: Verifying Design

Organization: RV-VLSI

Duration of Project in weeks: 8

Description: The design verified comprises RTL implementation of AHB-

Wishbone bridge and wishbone drives serial communication

modules like SPI,I2C and UART .The given test bench

architecture was implemented using UVM methodology and it

is verified by writing test sequences

Tools Used : QuestaSIM & Text editor (gedit).

Achievements:

Got State 1st place in Caroms in Inter Polytechnic sports meet in 2008.

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Personal Profile:

Name :G VISHNUVARDHAN YADAV

Date of Birth : 12/June/1989

Address :H:no:2-162, kunta street, pagidyala,kurnool - 518412

Father Name : GOLLA VENKATESWARLU

Nationality : Indian

Sex : Male

Languages known : Telugu, English

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