Engineering Design
Resume:
Piyush M. Chaniyara
Curriculum Vitae
Piyush M. Chaniya ra Permanent Address
M .Tech. VLSI Design Engineering Ramvadi, Goverdhan nagar
VIT University,Vellore-632014. B/H JalaramMandir, Keshod-362220.
State:Tamil Nadu Count ry: I ndia Dist. : Junagadh S tate: Gujarat Count ry:
I ndia
Email:p acent3@r.postjobfree.com
Contact No :+91-972*******
Piyush M. Chaniyara
Curriculum Vitae
Career Objective:
In tend to build a career with commit ted and dedicated people, which will
help me to explore myself fully and realize my potential with willingness to work as
a key player in challenging and creative environment.
Educational Qualification:
July 2013 – Continue M.Tech. In VLSI Design
• VIT University,Vellore
• CGPA 8.23/10(1st and 2nd Sem.)
June 2008 – June 2012 B.E. In Electronics and Communication Engineering
• Gujarat Technological University
• CGPA 8.38/10
May 2005 – May 2008 Class X and XI I Science
• Gujarat Secondary and Higher Secondary
E ducation Board
• 74.43% and 71.25% Respectively
Tools and P rogramming Language P roficiency:
Hard. Descriptive Language :- Verilog HDL
Scripting Languages :- PERL,TCL
Simulators and EDA Tools :- Cadence Vir tuoso,Cadence RTL Compiler,Cadence
ncsim,Cadence Encounter, ALTERA ModelSim 6.5b,
A LTERA Quatrus ii 9.1sp2, Keil (89C51), Proteus.
Assembly Languages :- 8085, 8086 and 8051 with coding in C in Keil
Operating Systems :- L I N UX(Red Hate), Windows (XP,Vista,7,8).
Academic Projects:
Design of Serial CRC generator and Development of Verification
E nvironment for Serial CRC Generator using Verilog H D L .
Description :- Develop verilog HDL Code for serial CRC generator and BFM(Bus
F unction Module), Checker module and testcases and Code coverage analysis is
carried out using Cadence nclaunch tool which includes b lock coverage,toggle
coverage and expression coverage .
D esign of pipelined H igh-speed 128 bit Key generation Unit and analyze
p hysical design flow using Cadence Encounter Tool.
Piyush M. Chaniyara
Curriculum Vitae
Description :- T his project design of high speed pipelined key generation unit was
developed with the help of S-box,R-Con values Verilog HDL and synthesize using
cadence RTL compiler and physical design steps like f loor planning,placement,
routing,post layout simulation performed in Cadence RTL Compiler.
Design Of Low Power M ultiplier Using UCSLA Technique
Description :- T his project presents the 19.28% reduction of power consumption the
V LSI design of Uniform carry select adder (UCSLA) based multiplier technique
w ith compared to the Variable carry select adder (VCSLA) based multiplier
technique. The synthesis is carried out using cadence RTL Compiler tool and
Design is mapped to TSMC 45nm technology library for analyzing Area, Power and
Delay.
Design And I mplementation Of F PGA Based Automated Temperatu re
Cont roller
Description:- T his project presents the FPGA based hardware implementation of
temperature monitoring and control system in real time environment. The design
uses FPGA (Field Programmable Gate Array) for the hardware implementation and
s imulated using Verilog-HDL (Modelsim) and implemented on Altera DE-1 Board
using Altera Quartus I I software tool.
D esign a T wo Stage Op-Amp and make Layout using Cadence Vi r tuoso
T ool.
Description:- I n this project the sizing(Width/Length)NMOS is calculated according
to given specification and simulated on Cadence Vi rtuoso Tool and generated
L ayout for the Op-Amp.
Develop a MAT LAB Code for Lee Algorithm for maze routing
Description:- I n this project MATLAB Code is developed for Lee Algorithm for
maze
r outing for physical design.
Vehicle Automation System
Description:- T his project is based on embedded system which measure parameters
of vehicle like speed, distance covered, fuel in tank and mileage and display on the
L CD with 89c51 micro controller. I t gives amount of fuel in the tank digitally in
d igits on LCD Display and also measure and display mileage of vehicle and
generate alert message before the vehicle goes under reserve condition.
M ini P rojects:
Rain Detector, F M Transmit ter, Window Detector
Piyush M. Chaniyara
Curriculum Vitae
Area Of I n terest:
• Verification and Testing, ASIC Physical Design, Analog I.C. Design.
Achievements:
• Achieved 1st r ank(out of 340 Students) in college in 7th semester during
Bachelor of Engineering.
• Achieved 3rd r ank (out of 66 Students)in class in 6th semester during
Bachelor of Engineering.
• Runners up in the badminton doubles in an int ra college sports week.
(2009)during Bachelor of Engineering.
• Achieved first rank on teacher’s day for power electronics, communication
engineering studies during Bachelor of Engineering.
• Qualified GATE(Graduate Apti tude Test in Engineering )-2013 and
GATE-2014.
Work Shops Attended:
• Ethical Hacking
Two Days workshop on ethical hacking by Sunny Vaghela at B. H. Gardi
College of Engineering & Technology, Rajkot on 2nd-3rd Feb., 2011.
• Digital Signal P rocessing
Two Days Work shop on Digital Signal Processing by Dr. Hemant Patil from
DA-I ICT,Gandhinagar at GCET-Rajkot. on 30th nov-1st Oct. 2011.
• Embedded Systems
Attended three days workshop on E mbedded system (AR M-7) by M r
J ivanbhai katariya, Director, SPJ Systems, Pune held at B. H. Gardi
College of Engineering & Technology, Rajkot.
Personal Details:
• Date of Bi rth : 27th A pril, 1991
• Hobbies : Swimming, carom, volleyball.
• Languages : E nglish, Gujarati, and H indi.
Strength:
W illingness to learn, strong determination, hard working, self motivated
Piyush M. Chaniyara
Curriculum Vitae
References:
M r. Arunkumr P. M r. C.D.Parmar
Assistant Professor, Head Of Department,
V LSI Division, SENSE School, Elect. & Comm. Engg Dept.
V IT University, Vellore B. H. Gardi College of Engg. &
Tech.,Rajkot
a acent3@r.postjobfree.com
acent3@r.postjobfree.com
D eclaration:
I hereby declare that the information furnished above is t rue to the best of my
k nowledge.
P iyush M.
C haniyara
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