Design Engineering

Location:

Posted:

June 12, 2014

Tuo Shan

BACKGROUND, OBJECTIVE

• Strong background in circuit and system design and testing. Looking for engineering positions in IC design and

verification.

HIGHLIGHTS

• CAD tools (Cadence, • Hardware and firmware • VHDL and Verilog language

Synopsys, Primetime) design • Perl script

• C, C++ expert • Test bench design • Quick learner

• Matlab trained • Teamwork

EDUCATION

M.S. Electrical Engineering May 2014 The University of Texas at Dallas

• GPA: 3.734/4.00

• Graduate Level Courses Advanced Analog IC Design, Power Management Circuits, High-speed Data

Communication Circuits and Systems, Computer Architecture, Advanced VLSI, Microprocessor Systems, Analog

Integrated Circuit Design, VLSI Design, Design Automation of VLSI Systems

B.S. Information Engineering June 2012 Shanghai Jiao Tong University

• 2012 Excellent Graduate Student Award

• 2011 Scholarship of Shanghai Jiao Tong University

EXPERIENCE

Computer Architecture Project UT Dallas 10/2013 – 12/2013

• Researched CPU performance of Alpha 21264 EV6 under different cache design choices using Simplescalar,

performed adaptive and effective searching and testing strategy by Perl script.

• Investigated different branch prediction algorithm by modifying the Simplescalar source code in C language,

optimized CPI performance in different branch prediction mode, BTB sizes, etc.

VLSI Projects Using IBM-130 Process UT DALLAS 09/2012 - 12/2012

• Designed a 1 K-bit SRAM including schematic, layout and simulation

• Designed a 23-bit by 23-bit multiplier, achieved smallest area among near 50 groups.

• Designed an IIR filter using Verilog HDL, synthesized by Synopsys and simulated by ModelSim and Primetime.

Research Volunteer Texas Analog Center of Excellence 05/2013 - present

• Measured and analyzed human EEG signals and do the signal processing with FPGA and MATLAB.

• Design ECG analog frond-end chip in GlobalFoundries-65nm process to realize real-time human ECG signal

sampling and analyzing.

• Designed a PN calibration, negative capacitor strategy and chopper-based LNA to cancel the motion artifact and

achieve 80dB CMRR and 10μV input-referred noise.

USB 3.0 Transceiver Project Using IBM-90nm Process UT Dallas 04/2014

• Designed a 5Gb/s, low jitter CP-PLL using IBM-90nm process with 1.2V voltage supply and 23mA total current

consumption.

• Designed a LC-VCO with 5GHz center frequency, realized -110 dBc/Hz phase noise.

• Designed a high-speed CML latch working at 5 GHz.