CURRIICULUM VIITAE

CURR CULUM V TAE

Mahdi Ahangariana bhari

E-mail: aceift@r.postjobfree.com

Cell Phone: +39-380-***-****

EDUCATION:

Current position: Postdoctoral researcher in Electronic Engineering, Department of

Electronics, Information Science and Bioengineering, Politecnico di Milano, Milan, Italy.

01/2011 - 12/2013: PhD in Electronic Engineering, Department of Electronics, Information

Science and Bioengineering, Politecnico di Milano, Milan, Italy.

09/2006 - 05/2009: M.Sc. (Honors) in Electronic (Analog) Engineering, Electrical

Engineering Department, Iran University of Science & Technology (IUST), Tehran, Iran,

(GPA: 18.38).

09/2002 - 09/2006: B.Sc. (Honors) in Electronic Engineering, Electrical Engineering

Department, K. N. Toosi University of Technology (KNTU), Tehran, Iran, (GPA: 15.98).

09/2001 - 07/2002: Pre-University, Certificate in Mathematics and Physics, (GPA: 19.56)

09/1998 - 07/2001: High School Diploma in Mathematics and Physics, (GPA: 19.43)

ACADEMIC HONORS & SCHOLARSHIPS:

Appreciated and Certificated in the National Mathematics Olympiad, 2001.

Appreciated and Certificated in the National Physics Olympiad, 2001.

Entitled as ‘Outstanding Student’ in National University Entrance Exam, September 2002.

Ranked 5th among 178 EE students of the department at BS Period, KNTU, July 2006.

Ranked 2nd Among MS Electronic Students of the department, IUST, October 2008.

Ranked 1st Among MS Electronic Students of the department, IUST, May 2009.

Received “ Educational Elite” Award, IUST, July 2009.

Availability:

Availability to Start:

One month after interview (the required time to leave my present job).

Availability to interview:

Monday to Saturday with an appointment.

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Scientific publications:

Published:

M. Ahangarianabhari, G. Bertuccio, D. Macera, P. Malcovati, M. Grassi, A. Rashevsky, I.

Rashevskaya, A. Vacchi, G. Zampa, N. Zampa, F. Fuschino, Y. Evangelista, R. Campana, C.

Labanti, and M. Feroci, “ A Low-Power CMOS ASIC for Large Area X-Ray Silicon Drift

Detectors Low-Noise Pulse Processing”, Journal of Instrumentation (JINST), Volume 9, Issue

3, pp. 1-8, March 1014.

M. Ahangarianabhari, and A. Abrishamifar, “A Novel Ultra Low-Power CMOS OTA with

Rail-to-Rail Operation,” International Journal on Information & Communication

Technologies (IJICT), VOL. 2, NO. 1 -2, pp. 113-116, January-June 2009.

M. Ahangarianabhari, G. Bertuccio, D. Macera, P. Malcovati, M. Grassi, G. Baldazzi, M.

Feroci, C. Labanti, A. Rashevsky, A. Vacchi, G. Zampa, N. Zampa, “Readout Front -End

Electronics for Large Area X-Ray Linear Silicon Drift Detectors for Space Missions”, IEEE

NSS/MIC/RTSD Anaheim, California, 27 October – 3 November 2012. (The paper won

conference trainee grant of $500 and presented at N6 -5 section).

M. Ahangarianabhari, G. Bertuccio, D. Macera, P. Malcovati, M. Grassi, A. Rashevsky, A.

Vacchi, G. Zampa, N. Zampa, C. Labanti, M. Feroci, “A Low-Power CMOS ASIC for X-Ray

Silicon Drift Detectors Low-Noise Pulse Processing”, the 15th IWORID workshop Paris,

France, 23–27 June 2013.

M. Ahangarianabhari, and A. Abrishamifar, “A Novel Ultra Low–Leakage Switch for

Switched Capacitor Circuits,” the 5th IEEE-GCC conference and exhibition, pp. 443 -447, 17-

19 March 2009.

M. Ahangarianabhari, and A. Abrishamifar, “A Novel Ultra Low-Power CMOS OTA with

Rail-to-Rail Operation,” International Conference on VLSI and Communication (ICVCom),

pp. 289-292, 17-19 April 2009.

M. Ahangarianabhari, A. Abrishamifar, and S. J. Azhari, “ Ultra Low-Power Super Class AB

CMOS OTA Cells with Rail -to-Rail Operation,” IEEE Latin American Symposium on Circuits

and Systems (LASCAS), pp.374 -377, 24-26 February 2010.

F. Fuschino, R. Campana, Y. Evangelista, M. Ahangarianabhari, M. Grassi et al.,

“Characterization of the VEGA ASIC dedicated to large area position-sensitive SDDs for

space and medical applications”, Proceeding of IEEE NSS/MIC/RTSD, 2013.

M. Feroci, …, M. Ahangarianabhari et al., “LOFT - the Large Observatory For x-ray

Timing”, Proceedings of SPIE, Instrumentation and Methods for Astrophysics, Vol. 8443,

Paper No. 8443-85, 7 September 2012.

S. Zane, …, M. Ahangarianabhari et al., “A Large Area Detector proposed for the Large

Observatory for X-ray Timing (LOFT)”, Proceedings of SPIE, Inst rumentation and Methods

for Astrophysics, Vol. 8443, Paper No. 8443 -87, 7 September 2012.

E. Bozzo, …, M. Ahangarianabhari et al., “The Large Observatory For X-ray Timing:

LOFT”, Proceeding of Science (PoS), 9th INTEGRAL Workshop and celebration of the 10t h

anniversary of the launch, Bibliotheque Nationale de France, Paris, France, 15 -19 October,

2012.

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L. Andreani, …, M. Ahangarianabhari, et al, “Characterization of a new gamma -ray

Detector based on 16x16 anode PSPMT coupled with LaBr 3Scintillator,” 2013 IEEE

NSS/MIC, 27 October – 2 November 2013, Seoul, Korea.

M. Feroci,…, M. Ahangarianabhari et al, “LOFT Assessment Study Report (Yellow Book),”

ESA/SRE, December 2013. Available online at: http://sci.esa.int/loft/53447 -loft-yellow-

book/#.

Accepted:

G. Bertuccio, M. Ahangarianabhari, C. Graziani, D. Macera, Y. Shi, A. Rachevski, I.

Rashevskaya, A. Vacchi, G. Zampa, N. Zampa, P. Bellutti, G. Giacomini, A. Picciotto and C.

Piemonte, “A Silicon Drift Detector - CMOS Front-End System for High Resolution X-Ray

Spectroscopy up to Room Temperature ”, the 16th IWORID workshop Trieste, Italy, 22–26

June 2014.

J. Bufon, M. Ahangarianabhari, P. Bellutti, G. Bertuccio, S. Carrato, G. Cautero, S. Fabiani,

G. Giacomini, A. Gianoncelli, D. Giuressi, M. Grassi, P. Malcovati, R. H. Menk, A. Picciotto,

C. Piemonte, I. Rashevskaya, A. Rashevski, A. Vacchi, G. Zampa, N. Zampa, “ A Novel

Multi-cell Silicon Drift Detector for Low Energy X-ray Fluorescence (LEXRF)

Spectroscopy”, the 16th IWORID workshop Trieste, Italy, 22 –26 June 2014.

Y. Evangelista, F. Fuschino, R. Campana, M. Ahangarianabhari, M. Grassi, Y. Favre, L.

Andreani, M. Zuffa, G. Baldazzi, G. Bertuccio, M. Feroci, C. Labanti, P. Malcovati, M.

Marisaldi, A. Rachevski, A. Vacchi, G. Zampa, N. Zampa, “Large-area linear Silicon Drift

Detectors for X-ray imaging and spectroscopy”, the 16th IWORID workshop Trieste, Italy, 22–

26 June 2014.

Submitted:

M. Ahangarianabhari, G. Bertuccio, D. Macera, P. Malcovati, M. Grassi, “VEGA: A Low-

Power Front-End ASIC for Large Area Multi -Linear X-Ray Silicon Drift Detectors: design

and experimental characterization” Nuclear Instrumentations and Methods A (NIM).

G. Bertuccio, M. Ahangarianabhari, C. Graziani, D. Macera, Y. Shi, A. Ra chevski, I.

Rashevskaya, A. Vacchi, G. Zampa, N. Zampa, P. Bellutti, G. Giacomini, A. Picciotto and C.

Piemonte, “Ultra Low Noise Silicon Drift Detector and CMOS Front -End for X-Ray

Spectroscopy with less than 100 eV Energy Resolution at Room Temperature”, IEEE

NSS/MIC/RTSD, SEATTLE – WA - USA, 8-15 NOV. 2014.

G. Bertuccio, D. Macera, C. Graziani and M. Ahangarianabhari, “ A CMOS Charge

Sensitive Amplifier with Sub-Electron Equivalent Noise Charge”, IEEE NSS/MIC/RTSD,

SEATTLE – WA - USA, 8-15 NOV. 2014.

A. Zappettini, G. Benassi, N. Zambelli, D. Calestani, G. Rotondo, B. Garavelli, P. Pozzi, D.

Macera, M. Ahangarianabhari, Y. Shi, G. Bertuccio, “High Energy Resolution Pixel

Detectors Based on Boron Oxide Vertical Bridgman Grown CdZnTe Crystals”, IEEE

NSS/MIC/RTSD, SEATTLE – WA - USA, 8-15 NOV. 2014.

To be submitted:

G. Bertuccio, M. Ahangarianabhari, D. Macera, Y. Shi, “ Noise analysis of a Silicon Drift

Detector for high resolution X-ray spectroscopy”, to be submitted to IEEE Transaction on

Nuclear Science.

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M. Ahangarianabhari, G. Bertuccio, D. Macera, “An Integrated Low-Power High-Precision

Peak stretcher/Sample and Hold Circuit,” to be submitted to IEEE Transaction on Nuclear

Science.

PhD Thesis:

“ Design, Simulation and Characterization of Low-Noise Low-Power F ront-End ASICs

for High Resolution X-ray Silicon Drift Detectors,”

1. The aforementioned project is in collaboration with University of Pavia, University of

Bologna, INAF/IASF Roma, INAF/IASF Bologna and INFN Trieste. The designed,

fabricated and characterized ASIC has recently been proposed for the LOFT mission (one

of the four candidates selected by ESA for Cosmic Vision M3 mission).

2. The design, simulation, fabrication and characterization of the low-noise, low-power FEE

has been carried out in 0.35 µm CMOS C35B4C3 Technology by AMS in single and 32

channels versions. The designed FEE is fully integrated and ADC ready. Single channel

version of the ASIC has been tested and characterized and all the functionalities have been

approved. The minimum intrinsic equivalent noise charge of 12 electrons r.m.s. is

measured for the full FEE at 3.6 µs shaping time and room temperature. The minimum

equivalent noise charge of 16 electrons r.m.s. at -30ºC is measured for the FEE circuit

loaded with 10 mm2 quad FBK SDD. Total power consumption of 480 µW is measured

for the single channel version of the ADC ready ASIC with dimensions of 200 µm 500

µm.

3. The advantage of the designed FEE is not only low-noise and low-power, but also fully

functional and ADC ready. The FEE circuit is designed and optimized for high-resolution

X-ray spectroscopy in the space with the required specifications of the LOFT mission. The

ASIC has recently proposed for the LOFT mission, which will launch 2020 -2022.

4. The 32 channels version of the FEE circuit without detector connected is tested at

INAF/IASF Bologna and the minimum intrinsic equivalent noise charge of 1 3 1 electrons

r.m.s. is measured. Total power consumption of about 13.5 mW (equivalent to ~422 µW

per channel) is measured for the multi-channels version of the ADC ready ASIC with

dimensions of 200 µm 500 µm per channel. Power consumption of the multi -channels is

lower than single channel due to the fact that the I/V references is shared between all

channels in the multi-channels version.

5. Measurements of the multi-channels version of the ASIC loaded with the first prototype

71 cm2 LOFT LAD SDD started in July 2013 at INAF/IASF Rome. The minimum

FWHM (full width half maximum) of 202 eV is measured on the Mn Kα line of the 55Fe at

-35ºC, which accomplish the required specifications of the LOFT mission . The

measurement results are recently (September 2013) presented at ESA and are published at

ESA/SRE (LOFT yellow book).

PhD Courses:

1. Nuclear Microelectronics.

2. High Speed Communication Circuits.

3. Semiconductor Memories.

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4. Non Volatile Memories.

5. Organic Electronics, Principals, Devises and applications.

6. Practicing Collaboration in Research.

M.Sc. Courses:

1. Analog Integrated Circuit Design.

2. Digital Integrated Circuit design.

3. Application of Analog Integrated Circuits.

4. VLSI Circuits.

5. Theory and Technology of Fabrication of Semiconductor Devices.

6. Digital Signal Processing.

7. Optoelectronic.

Additional Research:

3 months additional research duri ng PhD degree (July-October 2012):

“Electrical Characterization of Graphene Transistors and Graphene Ring Oscillators,”

M.Sc. Thesis:

“ Design and Simulation of CMOS Image Sensor with High Dynamic Range and Low-

Power Consumption,” which I got the highest grade, 20 out of 20 (20/20).

WORK EXPERIENCES:

Postdoctoral researcher in field of microelectronics at Politecnico di Milano University. It is

my current working and research position which started in January 2014.

Teaching Assistantship for two semesters at K. N. Toosi University of Technology (IUST),

Under Prof. Hosein Hoseininejhad supervision, fall 2005- spring 2006.

Fundamentals of Electronics

Electronics II

Lab-Electronics I, II, III

RESEARCH & PROJECTS:

PhD Thesis: “ Design, Simulation and Characterization of Low-Noise Low-Power Front-End

ASICs for High Resolution X-ray Silicon Drift Detectors”.

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PhD Minor Research: “Electrical Characterization of Graphene Transistors and Graphene Ring

Oscillators”.

M.Sc. Thesis: “ Design and Simulation of CMOS Image Sensor with High Dynamic Range and

Low-Power Consumption”.

B.Sc. Project: “Simulation and Design of First 10 Fourier Harmonics Generator”.

PRESENTATIONS:

“ A Low-Power CMOS ASIC for X-Ray Silicon Drift Detectors Low-Noise Pulse Processing”,

the 15th IWORID workshop Paris, France, 23 –27 June 2013.

“Read-out Front-End Electronics for Large Area X-Ray Silicon Drift Detectors for Space

Missions,” IEEE NSS/MIC/RTSD, Anaheim, California, USA, 27 October – 3 November 2012.

“The Front-End Electronics for LOFT/XDXL Drift Detectors,” Presentation on the

measurement results of the single channel ASIC proposed for LOFT/XDXL SDD ASIC

meeting, IASF, Bologna, 26 September 2012.

“ A Novel Ultra Low–Leakage Switch for Switched Capacitor Circuits,” the 5th IEEE-GCC

conference and exhibition, 17-19 March 2009, Page(s):443 -447, Kuwait.

“ Design, Simulation and Characterization of Low-Noise Low-Power Front-End ASICs for

High Resolution X-ray Silicon Drift Detectors,” the second year evaluation of the PhD

degree, Politecnico di Mi lano, December 2012.

“Electrical characterization of graphene transistors and graphene ring oscillators,” November

2012, Politecnico di Milano - Como campus.

“ Low-Noise Low-Power Front-End Electronics for Large Area X-ray Silicon Drift Detectors

for Space Missions,” 28 September 2012, 5th PhDAY, Politecnico di Milano, Milan.

“ Design, Simulation and Characterization of Low-Noise Low-Power Front-End ASICs for

High Resolution X-ray Silicon Drift Detectors,” the first year evaluation of the PhD degree,

Politecnico di Milano, November 2011.

“ Design and Simulation of CMOS Image Sensor with High Dynamic Range and Low-Power

Consumption,” M.Sc. Thesis, IUST, May 2009.

“Analog Memories,” M.Sc. Seminar, IUST, May 2008.

“ Simulation and Design of First 10 Fourier Har monics Generator,” B.Sc. Project,

KNTU, September 2006.

SOFTWARE & LANGUAGE PROGRAMMING SKILLS:

Excellent skills in

Cadence

Origin

H-spice

L-Edit

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P-spice

MATLAB

ORCAD

Pad2Pad

Programming C/C++

Microsoft Office

Operating Systems: DOS, Windows (98, 2000, XP, Vista,7)

Typesetting: Microsoft Word

Familiar with

Assembly (Z80, 80x88 and 80296)

Programming C#

PROTEL

Assembly (8051, 80x86 and 80196)

T-spice

RESEARCH INTERESTS:

Analog, digital and mixed-signal IC design.

Low-power, low-noise analog IC design.

Low-noise, low-power, wide dynamic rage operational amplifier design.

Ultra low-noise, low-power charge sensitive amplifier design.

LANGUAGES:

Fluent in English (Overall Score of IELTS: 6.5)

Native Persian

Familiar with Italian

D.O.B:

31st, March, 1984

REFERENCES:

1. Prof. G. Bertuccio: aceift@r.postjobfree.com

2. Dr. D. Macera: aceift@r.postjobfree.com

3. Dr. Yuri Evangelista aceift@r.postjobfree.com

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ATTACHMENTS:

1. PhD Cetrificate

2. M.Sc. Certificate

3. B.Sc. Certificate

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Contact this candidate