Power Design
Resume:
Kalluri Rakesh
Email:******.*********@*****.***. Mobile: +917*********
Objective:
To devote my skills and knowledge for the fulfillment of the company’s goal and to
learn new technologies & techniques in physical design to enhance my skills and abilities.
Professional Training and Exposure:
• 6 months of exposure to ASIC Physical Design (Hierarchical/Flat design flow)- Floor
Planning, Power Planning, Place & Route, Clock Tree Synthesis, Timing Closure, SI
analysis, & DRC/LVS at Institute of Silicon Systems Pvt Ltd
• Solid Understanding of basic Electronics.
• Expertize in block level place and route on TSMC 130nm and 90nm technologies.
• Good Knowledge in Timing Analysis, Crosstalk Analysis, IR Drop Analysis & EM.
• Experience in standard cell layout design.
Hands on Tools:
• Cadence SOC Encounter - Floor Planning, Place & Route, and clock tree
synthesis.
• Encounter Timing System - Static Timing Analysis and Crosstalk Analysis.
• RTL Compiler - Logic Synthesis.
• Assura- Physical Verification.
• Virtuoso - Custom layout.
• Programming skill in VHDL& Verilog.
Technical Skills:
• Programming Languages : C, Matlab, TCL(Basics)
• Operating Systems : Windows Xp/7/8, Linux.
Education Details:
• First Class in Bachelor of Technology (ECE) with 67.7% from JNTU HYD
during 2009-2013.
• Intermediate with 81.0% from Board of Intermediate (2007-2009).
• Distinction in S.S.C with 81.00% from Board of Secondary Education during
2006-2007.
Projects:
PCI_DATA (TOP LEVEL):
Objective : Timing Driven Layout
Tools : SOC Encounter, ETS.
Gate count/Area : 1, 28,920/ 1572423.4 um^2
Macros /STD Cells : 12/24461
No. of Clocks : 8
Frequency : 150MHz
Technology/Layers : UMC 0.18 micron/5 Metal Layers
Role: Die size, PG planning, Performing sanity check, Design import, Floor Plan, Power
Plan, Placement, Trial Route, Power Analysis, RC Extract, Timing analysis, IPO, CTS,
Detailed routing.
(BLOCK LEVEL):
Objective : Timing Driven Layout
Tools : SOC Encounter, ETS.
Gate count/Area : 3,03,884/ 1547443.2 um^2
Macros /STD Cells : 12/27061
No. of Clocks : 17
Frequency : 200MHz
Technology/Layers : TSMC 0.13 micron/5 Metal Layer
Role:Performing sanity check, Design import, Floor Plan, Power Plan, Placement, Trial
Route, Power Analysis, RC Extract, Timing analysis, IPO, CTS, Detailed routing.
BRX-TOP (BLOCK LEVEL):
Objective : Timing Driven Layout
Tools : SOC Encounter, ETS.
Gate count : 11000
No. of Clocks : 3
Frequency : 150MHz
Technology/Layers : TSMC 0.18 micron/5 Metal Layers
Role:Performing sanity check, Design import, Floor Plan, Power Plan, Placement, Trial
Route, Power Analysis, RC Extract, Timing Analysis, IPO, CTS, Adding filler cells, Timing
Analysis.
LOGIC SYNTHESIS:
Tools : RTL Compiler
No of clocks : 2
Frequency : 200MHz
Role: Prepared Constraint file,TCL file, Performed Wireload and Zero Wireload Model
Timing Checks.
LAYOUT:
Standard Cells Layout Designing
Tools : VirtuosoLayout Editor, Assura Verification.
Design : Layout of a CMOS gates.
Role: Drawing the stick diagram from spice net list, drawing layout and verifying DRC and
LVS.
Academic Project Details:
Title : NETWORK DESIGNING USING EIGRP
Tools : Cisco packet Tracer
Project Description:
The project is about designing a ip network for routing the packet from source to
destination. This is mainly used in routers designed by CISCO. This is very easy to design
and manage.
Strengths:
Self Motivation, Optimistic, responsible, reliable, confident and dynamic.
Can handle changes and challenging situations.
Ability to work in a group as well as independently with minimal supervision.
Can mingle and deal with people properly.
Quick learner and ability to work in group.
Personal Profile:
Father's Name : Upender
25th March 1991
Date of Birth :
Marital Status : Single
Nationality : Indian
Languages : English, Telugu, Hindi.
Contact Address : S/o Upender
Yousuf Guda, Hyderabad (dist), AP.
Pin Code: 500045.
Declaration:
I hereby declare that the information that is provided above is up to date and true.
Place:
Date: (RAKESH.K)
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