Quality Assurance Manager

VENKATESHWARLU NERELLA

Email Id: **************.*******@*****.*** DOB: 10-02-1991

Mobile no: 91-991******* Sri Sai P.G, Marathahalli, Bangalore-560037

Career Objective

To obtain a position within an organization that will allow me to utilize my technical

skills, experience and to enhance my knowledge that will help to meet the company goals and

objectives.

Summary

• Graduate technical intern in PDK Development team at LSI Corporation.

• Final year M.Tech candidate with strong academic background.

• Motivated team player and individual contributor with excellent interpersonal and

communication skills.

Educational Qualification

Duration/

Marks/

Class/Course Name of Institute Board/University Year of

CGPA

passing

M.Tech National Institute of National Institute of 2012-2014 8.48 out of

(VLSI-SD) Technology, Technology, Warangal 10

Warangal

B.E Chaitanya Bharathi

(Electronics & Institute of

Osmania University 2008-2012 85.84%

communication Technology,

Engineering) Hyderabad

Sri Chaitanya Jr.

Class XII Board of Intermediate

College, 2006-2008 95.90 %

(M.P.C) Education, AP

Hyderabad

A.P.R.S,

Class X SSC 2006 94.66 %

Sarvail

Technical Skills

Languages Verilog, VHDL, C, SKILL, Shell & Perl

scripting

EDA Tools Cadence Virtuoso, Xilinx ISE Modelsim,

Calibre DRC/LVS, Tanner

Operating Systems Linux, Windows

• Automated DRC QA Regression Flow using Perl scripting for 16nm, 28nm tech nodes.

• Good at Calibre DRC Rule writing with SVRF format.

• P-Cell Qualification tests using SKILL coding

• Validated LSI custom design rules (for 16nm) by creating layout test cases.

Internship Project(June 2013-present)

AUTOMATION OF DRC TEST SUITE FOR DRC QUALITY ASSURENCE

Duration: M.Tech final year

Tools and Language: Cadence virtuoso layout editor, Calibre DRC, Cadence SKILL

language.

Description: Creating DRC ESD _LUP test cases by looking at DRM manually takes more

time. If we create generic structure with skill script we can reuse the same program script for

other rules also. With script we can accurately create the test cases, i.e. without missing any

false violation. The same script can be used for any technology nodes; we just need to change

the variables like minimum separation, power/ground labels, etc.

• Developed Perl script to submit all the calibre DRC runs to LSF machines

automatically for any no. of designs by covering all verisub options to do DRC regression

Quality Assurance for 16nm, 28nm technology nodes.

• I developed ESD and LUP test cases using SKILL script.

Academic Projects:

1. Design of fully compensated OP-AMP for the following specifications

Gain = 100db, UGB = 10MHz, Phase Margin = 87

Tool: Cadence 180nm

2. Implementation of 32-bit single cycle MIPS Processor.

Implementation includes a subset of core MIPS instruction set; R – type, load type, store type

and branch instruction.

3. Remote Control Operation of Multiple Transceivers through an E1 Radio Inter

Connect and its Manual Testing.

DIGITAL V/UHF radio transceivers are software controlled multimode radios providing

transmission and reception between 100 MHz to 399.975MHz in areas of civil air traffic,

maritime and military applications. DIGITAL V/UHF radios are operated in LOS (Line of

Sight) with EPM (electronic protection measures – ECCM) mode or VOIP (voice over

internet protocol) for communication. In manual testing, we verify the transmitter/receiver

specifications.

Duration: B.E Final Semester

Internship at ELECTRONICS CORPORATION OF INDIA LIMITED

Achievements

• School topper in SSC Examination.

• Received PRATHIBA Award in 10th class.

• Topper in M.Tech 1st Sem.

• Selected for intern presentation contest at LSI

• Got N.C.C-A Certificate and camp certificate.

References

1. Name: Shiva Kumar Kotikalapudi,

Designation: ASIC DvDs Engineering Manager Senior, LSI.

Contact:*****.************@***.***

Declaration:

I hereby declare that the above mentioned details are true to the best of my knowledge.

Signature:

N.Venkateshwarlu

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