Graduate student seeking full time opportunity as Jr. FPGA Engineer

Arihant Sampatlal Singhvi

**** *********** **, *** ****, California 95131

Cell: 312-***-****, Email: ********.*******@*****.***, LinkedIn: www.linkedin.com/in/arihantsampat/

Objective

Seeking a full time opportunity, where I can implement my knowledge and experience in circuit design, Functional Verification and Synthesis

Education

Master of Science – Electrical and Computer Engineering

May 2014

University of Illinois at Chicago (CGPA – 3.78/4.00)

Bachelor of Engineering – Electronics and Communication Engineering

April 2012

Anna University (CGPA – 8.22/10.00)

Key Skills

Programming Languages

HDL - Verilog and VHDL;

Scripting - TCL and Perl;

Basics - C, C++, Assembly Language (Intel 8051/Intel 8086) and SPICE

Design Tools

Synopsys - VCS-MX, Design Compiler (DC), HSPICE and CosmosScope;

Cadence - NcSim, and Virtuoso;

Altera - Quartus II and ModelSim;

Engineering

RTL Design, Functional Verification, Synthesis, Simulation, Static Timing Analysis, Custom

Circuit and Layout design, MOSFET and FinFET based CMOS design, SRAM cell design,

Pipeline Concept, Computer Architecture, Cache and Design for Test (DFT) principles

Operating System

Red Hat Enterprise Linux 5.9 and Windows 8/7/XP

Courses Taken

Digital Design, Introduction to VLSI Design, Advanced VLSI Design, Integrated Circuit Engineering, Analog and Mixed VLSI Design, Advanced Computer Architecture, High Performance Processors and Architecture, Testing and Reliability of Digital System, Nanoelectronics and Network Analysis

Work Experience

AXIIP Semiconductor Pvt. Ltd, Chennai, India

December 2013 – January 2014

ASIC Design Intern

- Programmed Serializer and Deserializer interface segment of V-by-One HS Standard using Verilog HDL

- Encoded the CRC segment in Safe-by-Wire Plus design using Verilog HDL

- Scripted using TCL on Red Hat Enterprise Linux 5.9 Platform

- Gained a good exposure in writing Test Bench in Verilog HDL

- Tools used for Functional Verification: - Synopsys VCS-MX and Cadence NcSim; Synthesis: - Synopsys Design Compiler (DC)

Related Project Experience

Design of FinFET based SRAM Cell for 22nm Technology

March 2014 – April 2014

- Coded 1 bit SRAM cell design using FinFET model from BSIM-CMG version

- Simulated the designed SRAM Cell in Synopsys – HSPICE and plotted the result in CosmosScope

- Compared and analyzed the working of SRAM cell design using PTM model of MOSFET and FinFET in 22nm scale

Design of MOSFET based 4-bit Arithmetic Logic Unit for 0.25um Technology

September 2012 – November 2012

- Designed (Schematic and Layout) 4-bit Arithmetic Logic Unit (ALU) along with its simulation at 1GHz clock frequency

- Various functions like Carry Look Ahead Adder, 1’s and 2’s Complement, Add-traction, 4 to 1 Multiplexer and D Flip Flop were implemented at CMOS level Layout, Extraction and Verification (DRC/LVS) were done using Cadence Virtuoso

- Eliminated minimum hold and setup time failure by performing Static Timing Analysis

Design for Test (DFT) – Performing Test Vector Reduction

April 2013 – May 2013

- Attained test vector reduction for ISCAS89 scan chain files by using Compaction and Compression technique; executed in Atalanta-M tool

- Developed Random Vector Elimination algorithm in Perl language to perform test vector compaction Coded Run Length Encoding Technique to perform compression and decompression of compacted test vectors

- Minimized hardware cost around 89% by devising parallel-series type Architecture for Circuit Under Test (CUT) and Scan Chain Cells

Implementation of Cache Replacement Policy

October 2012

- Modified the width size of fetch, decode and commit stages; observed their varying performances

- Implemented new cache replacement policy Most Recently Used (MRU) using C language

Compared the overall performance and cache miss rate of four different cache replacement policy : - Least Recently Used (LRU), First In First Out (FIFO), Random and Most Recently Used (MRU)

16 Bit Kogge Stone Adder

September 2012

- Encoded a 16 Bit Kogge Stone Adder in VHDL and Verilog HDL

- Classified the 16 Bit value into 5 layers to calculate at a faster rate

- Simulated and synthesized in Altera Quartus

Activities

- Public Relation Representative of UIC – International Club (IC)

- ECE Department Representative for Graduate Student Council at UIC

- Member of Indian Graduate Student Association (IGSA) at UIC

- Executive Member of Akhil Bharatvarshiya Sadhumargi Samta Yuwa Jain Sangh, India

- Event Organizer of departmental symposium – Elexrieg’11 at MNM Jain Engineering College, India

- Headed as Academic Coordinator at MNM Jain Engineering College, India (2008-2012)

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