415-***-**** aceb3r@r.postjobfree.com

http://www.linkedin.com/in/mahidharnandigam/

MAHIDHAR NANDIGAM

****, **** ***, *** *********, CA 9411

OBJECTIVE

Obtain a position as Hardware Design and Verification Engineer where I

can grow professionally and further enhance my skills, knowledge, and

experience in a company that is looking to push the boundaries and shape

challenges of tomorrow.

SKILLS

. Proficiency in Programming Languages: C/C++, VHDL, Verilog, Assembly

Language, Matlab, Java.

. Experience in SystemVerilog, VMM, OVM/UVM test methodologies.

. Knowledge in Audio Video Codec: MPEG1/2/4, H264, JPEG, MJPEG,

JPEG2000.

. Excellent knowledge in Algorithm, System and SIMD Optimization DCT,

IDCT, FFT, motion estimation/compensation, image deinterlacing,

interpolation, audio/video filtering, pattern recognition,

. Working Knowledge on Interconnect Protocols: PCIe, PCI/X AXI AHB, APB,

and I2C.

. Hands on experience with ASIC Tools: Aldec Riviera-PRO, and tools from

Cadence, and Synopsys.

. Expertise knowledge in FPGA Tools: Xilinx ISE, Active HDL, Synplify

Premier, ModelSim, VCS, ChipScope, PlanAhead, Altium.

. Familiarity with Scripting Languages: Python, Ruby, Perl.

. Familiarity with Schematic capture and PCB layout tools.

. Ability to use oscilloscopes, logic analyzers, peak power analyzers,

and network analyzers.

EDUCATION

George Mason University Fairfax, VA Master's of Science in Computer

Eng., Jan 2011- Dec-2012

Cumulative GPA: 3.50/4.00

Courses: Cryptographic Engineering Computer Arithmetic DSP Hardware

Architecture Digital System Design Embedded systems

Hardware/Software co-design Device Drivers Real Time OS Computer

Networks High-speed RF Signal Theory Digital Circuit Design.

Old Dominion University, VA. Master's of Engineering in Computer Eng.,

Jan 2007 - Dec 2010

Cumulative GPA: 3.51/4.00

Courses: Analog and Digital VLSI Computer Arithmetic Design ASIC

Designing Parallel Computing Statistical Analysis and Simulation

Computer Networks like PHY or MAC schemes and protocols like Ethernet

Layer 2 and 3 protocols Mixed-Signal IC Designs. Mixed-Signal and

DSP Techniques.

Andhra University INDIA. Bachelors of Science in Electrical and

Communications Eng., May 2006

Cumulative GPA: 3.75/4.00

WORK EXPERIENCE

ELAN Technologies (Jan 2014 - Present)

Consultant

. Responsible for the daily QA activities. Monitor the successful

completion of the quality initiatives at every step of the Software

Development Life Cycle SDLC.

. Organized, planned and managed test case development and execution

effort.

. Initiated configuration management test case development process.

. Co-wrote project Test Plan, Test Case for Execution phase, identified

and documented volumes of production impacting software defects. All

defects resolved within required time-line.

. Methodologies: QA Black Box, White Box Testing, Understanding of JAVA

test tool, JTEST and test framework JUNIT and JAVA knowledge and

concepts, Full System and QA Lifecycle, all phases and deliverables

Qualcomm Semiconductors (March 2013 - Dec 2013)

CPU Verification Engineer

. Architecture verification of the TOP and CPU of the next generation

Qualcomm's ARMv8 and ARMv7 compliant processor.

. Developed tests to verify ICACHE commands in ARM architecture.

. Provided solutions to bridge OVM/UVM based test suite with DV team's

testbench.

. Created new OVM/UVM based components new design to ensure functional

coverage.

. Currently writing functional verification tests for 64-bit ARM based

processor based on specifications.

. Generated tests using Perl and Perl modules.

George Mason University - Dept. of Applied Information Technology (2011

-2012)

Teaching Assistant

. Taught graduate topics likes: Problem solving with Programming

Language: Java and Computer Hardware.

. Performed task from grading assignments to conducting exams to taking

substitution class.

GE Intelligent Platforms - Control Communication System (Sep 2008 - Dec

2008)

Intern Test Engineer

. Assisted in developing Testware for PAC Motion Modules (PMM) PLC with

motion module

. Worked in a highly experienced team to run the different System Tests

on PMM.

. Developed an Ad hoc manual test without any assistance.

Old Dominion University - Department of Electrical and Computer Eng.

(2010 & 2008)

Research Assistant

. Developed scripts to automate the modeling of the OFFSHORE WINDFARMS

using Java and Perl.

. Simulated electrical components, which were directly used for the

optimization of Cost Function of Wind farms

. Implemented Geometric algorithm using Symbolic toolbox in Matlab for

optimizing of the offshore wind farms.

. Devised a holistic solution for the design of offshore wind farms and

suggested the usability of Genetic Algorithm which lead to the actual

research.

. Published an IEEE paper "Optimal Design of an Offshore Wind farm

layout".

PROJECTS

Remote Device Controller using GSM Network

. Developed Microcontroller Driver for communication between GSM-Based

Network and ATMEL microcontroller.

. Was involved in all aspects of the project from specifications to

implementation to verification.

. Used Nokia FBUS protocol to send and receive text messages.

. Technologies used: micro-controllers, GSM Network, Kiel Compiler, and

Embedded C.

FPGA Implementation of 512-bit Grostl: A SHA-3 Candidate. (2010- 2012)

. Designed Basic, Folded, Parallel, and Pipelined architectures and

implemented them in Verilog.

. Implemented test models in C++ and Java to attain reference

performance measures.

. High throughput core was synthesized on Spartan 6 FPGA.

. Implemented test bench using UVM methodologies.

. Integrated assertion based verification using System-Verilog as part

of experiment.

Hardware Implementation of Lightweight 256-bit Hash function: Lesamnta-LW

(2011)

. Implemented lightweight hash function on three FPGA platforms: Virtex

5, Spartan 3 and Stratix III.

. Designed the round function using Galois Field multiplication.

. Writing PCIExpress interface at the block level to match IP frequency.

. Optimized the implementation for maximum throughput and minimum area

using GMU optimization algorithm

Implementing Superscalar Microprocessor with Out-of-Oder execution. (2008-

2010)

. Designed and assisted with construction of the MIPS processor

architecture with Out-of-Oder execution.

. Part-Designed the control logic with an innovative idea to implement

multiple instructions per second.

. Architecture was build using Tomasulo Algorithm.

. Technologies used: VHDL

WORK IN PROGRESS

Verification of Asynchronous FIFO (2014)

. To do functional verification of FIFO with clock domain crossing.

. Developed an uvm_env from scratch, including Sequencer, Monitor, and

Driver.

. Used OOP concepts in writing verification code for reusability.

. TLM in OVM for SystemVerilog.

Implementation of Nonlinear Adaptive Filters in FPGA (2012)

. Implement adaptie FIR filter in Matlab and using Neural Networks as

nonlinear function.

. Realize this filter in FPGA and compare architecture designs like

pipelined, parallel and retiming.

. Utilize this design in a real-time application upon pre-processed data

is acquired.

REFERNCES

NATH A N DE E S E Qualcomm aceb3r@r.postjobfree.com (919)

297-3232

Dr. Kris Gaj GMU aceb3r@r.postjobfree.com (703)

993-1575

Dr. JENS-PETER KAPS GMU aceb3r@r.postjobfree.com (703)

993-1611

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