Junpeng Feng
** ******* ***, ******, ** ***** 617-***-**** acea5s@r.postjobfree.com
EDUCATION
Northeastern University, Boston, MA, U.S.A
Graduation: Dec. 2013
. M. S. in Electrical Engineering
. Relevant courses: RF Integrated Circuit Design, Analog Integrated
Circuit Design,
Solid State Devices, VLSI Design,
MEMS.
Shenyang University of Technology, Shenyang, Liaoning, P.R.CHINA
Jul. 2009
. B.S. in Electrical Engineering
. Relevant courses: Analog Circuit Analysis, Digital Circuit Analysis,
Circuit Analysis,
C Programming, Signal and System, MCS-
51single chip assembler language,
Principle of Automatic Control,
Electromechanics, DC/AC Motor Control.
TECHNICAL SKILLS
CAD software: Cadence Spectre, Cadence Virtuoso Schematic Editor, Cadence
Layout Editor, Calibre tools, HSpice,
PSpice, MATLAB SIMULINK, Protel 99SE.
PCB Design tool: KiCad.
Operating systems: Windows, Linux, Mac OS.
Desktop Application: Microsoft Office.
Computer languages: C/C++, Assembly language for MCS-51.
THESIS RESEARCH
. Temperature sensor for on-chip measurement of gain and power dissipation
of RF circuits.
. Finished the design, simulation, tapeout, PCB design, soldering,
measurements.
. Familiar with TSMC 0.18 m CMOS technology and Dongbu 0.11?m CMOS
technology.
. Know how to use Spectre of Cadence tools for layout and simulation.
. Learned the transimpedance amplifier (TIA) design.
. New temperature sensor design with low power consumption (0.6mW), wider
dynamic range and higher sensitivity than previous versions.
. Obtained analog IC design, tapeout, and measurement experience.
PROJECTS
A. Sample and Hold design (Ongoing)
. Design a Sample-and-Hold for a 500MHz input signal and 1GHz sampling
frequency.
B. High gain amplifier design
. Use of Miller compensation.
. Class AB output stage design (open-loop gain: 92dB).
. Three-stage amplifier design with 0.18?m TSMC CMOS technology.
. Common-mode feedback (CMFB) to stabilize the operating point.
C. Attenuator Design for OTA
. Attenuate the voltage swing from Vpp=1.2V to Vpp=40mV.
. Limited error on different corner of process variation and under
-30 C~85 C.
. Voltage regulator with bias current control circuit.
D. Common-Gate LNA with Gm-boosting
. Finished its design and layout using 0.18?m CMOS technology.
. Operating at 2GHz.
E. Double-balanced Mixer Design
. Input baseband signal: 990MHz, Output signal: 10MHz, Local Oscillator:
1GHz.
. Conversion gain: 12.58dB at 10MHz, Noise Figure: 16.64dB, IIP3:3.06dBm.
F. Low power, low phase noise VCO design
. Tuning range:1.73GHz-2.2GHz
. Power consumption: 1.967mW, Total Harmonic Distortion (THD): 5.36%.
. Phase noise: -80.1dBc/Hz at 10KHz offset, -128.1dBc/Hz at 1MHz offset.
F. 16-bit multiplier
. Implemented in 90nm CMOS technology.
. Finish its Layout and DRC, LVS checking in Cadence.
. Verified using HSpice.
G. Doubly-fed Induction Motor Flux Linkage Optimization (Undergraduate
Project)
. Learned the skills of Simulink simulation under MATLAB.
. Optimized and stabilized the flux linkage of doubly-fed induction
motor.
. Understand the approach of using doubly-fed motor in Hybrid-Electric
Vehicle.
CONFERENCE/WORKSHOP PUBLICATION
Accepted:
J. Feng and M. Onabajo, "A wide dynamic range temperature sensor for On-
Chip power monitoring", submitted to 2013 IEEE North Atlantic Test Workshop
(NATW).
JOURNAL PUBLICATION
Invited and Accepted:
J. Feng and M. Onabajo, "Wide dynamic range CMOS amplifier design for RF
signal power detection via electro-thermal coupling," Springer J.
Electronic Testing (JETTA): Theory and Applications, vol. 30, no. 1, pp.
101-109, Feb. 2014.
POSTER PRESENTATION
J. Feng and M. Onabajo, "A Wide Dynamic Range Temperature Sensor For On-
Chip Power Monitoring," Research and Scholarship Expo, Northeastern
University, March, 2013.
JOURNAL/CONFERENCE REVIEW
Journal reviewer for:
Nanoscience and Nanotechnology Letters, ISSN: 1941-4900 (Print); EISSN:
1941-4919 (Online).
Conference reviewer for:
ACM (Association of Computer Machinery) Great Lakes Symp. on VLSI
(GLSVLSI), 2014.