Engineering Electrical

Summary

Responsible for design, verification, and test of complex

electronics; specifically, Field Programmable Gate Arrays

(FPGA) using Hardware Design and Verification Languages

for the US Army Aviation & Missile Research, Development

and Engineering Center (AMRDEC), Software and Engineering

Directorate (SED).

I design and implement Universal Verification Methodology

(UVM) based verification environments for digital designs

using SystemVerilog, SystemC models with a focus on

hardware/software cosimulation, and both constrained

random and directed testing, with a focus on functional

coverage closure.

Languages

VHDL, Verilog, SystemVerilog, SystemC, TCL, Perl, Make

Tools

Aldec Riviera Pro, Aldec Active HDL, Mentor Graphics

Questa, Modelsim, UltraEdit, Microsoft Source Safe,

Visio, Matlab, Simulink, Microsoft Windows

Security Clearance: SECRET

Professional Experience

Dec 2007 - Present Intuitive Research and Technology Corporation (INTUITIVE),

Huntsville, Alabama

I designed, implemented, and verified a 1553 Transfer

Agent, an interface component for a DDC Bus Controller. I

used the component requirements to formulate the required

covergroups to achieve functional verification, and

interface and bound DUT assertions to shield from design

bugs and protocol errors.

I designed, implemented, and verified a User Datagram

Protocol (UDP) based "Link/Network Processor" (LNP) for

performing a subset of Network Layer IP functions on an

Ethernet based communication board. It implements Address

Resolution Protocol (ARP), Internet Control Message

Protocol (ICMP), and UDP. I chose an Algorithmic State

Machine (ASM) implementation, which resembles an embedded

processor; it contains: states values in dedicated DPRAM,

an Arithmetic Logic Unit (ALU), address stack, and a

next-state calculator. It allows for implementing

processor-like functionality for applications requiring a

large number of non-trivial states. The state transition

table for an ASM is described in a language very similar

to Assembly.

I designed and demonstrated an Inter-range Instrumentation

Group (IRIG) component for transmitting serial telemetry

data. It supports all six IRIG compatible line codes (Non

Return to Zero (NRZ) mark/space etc.), was ASM based, and

interfaced to a standard memory mapped bus.

I designed an Abstraction Layer Module (ALM), a component

which served as a bus master; in a multi-component digital

design; it handled top-level arbitration, initialization,

and data transfers between Ethernet, RS422, MIL-STD-1553,

and RS232 drivers.

I developed an embedded processor design using the Xilinx

MicroBlaze for a Spartan FPGA, and the corresponding C

code. It was successfully interfaced to a soft-core

Xilinx MAC at 10/100 speeds, Media Independent Interface

(MII).

I designed a 16550 compatible logic interface which allows

other logic elements to connect to an Industry Standard

Architecture (ISA) bus, and appear to the ISA host driver

as a 16550 UART.

I designed a keypad interface which receives user input

from a keypad and converts the inputs to ASCII characters

which are transferred to an ISA bus via the driver

previously mentioned.

Feb 2006 - Nov 2007 Integrated Power Technologies (IPT)

Madison, Alabama

Job Description:

Performed analog/digital circuit design and analysis

including Printed Circuit Board (PCB) Layout using OrCad

Conducted fault analysis on the Analog / Digital IO (ADIO)

card for the Digital Vehicle Distribution Box (DVDB)

system for the Bradley fighting vehicle.

Application details:

Designed and implemented a controller for an oxygen

concentrator. This PIC-based controller cycled power for

a pneumatic value and a compressor.

I assisted in design and implementation of Modular

Wearable Computer (MOWC) involving lightweight RGB touch

screen, power supply and a ruggedized computer, including

external USB and serial ports.

Sept 2005 - Jan Scientific Research Corporation (SRC)

2006

Huntsville, Alabama

Job Description:

Integrated threat systems, radar jamming simulation and

basic radar processes.

Jan 2003 - Mar 2004 Future Design, Inc. (FDI)

Huntsville, Alabama

Job Description:

As an associate engineer, I assembled FDI evaluation board

kits consisting of both surface mount and through-hole

components. Provided customer technical support relating

to specifications.

Education

Sept 2001 - Aug University of Alabama in Huntsville

2005

Huntsville, Alabama, USA

Bachelor of Science and Engineering

Electrical Engineering

GPA: 3.9

Aug 2008 - May 2011 Huntsville, Alabama, USA

Masters of Science and Engineering

Electrical Engineering

GPA: 3.8

Other

Digital Electronics Lab Instructor

Jan 2011 - May 2011 Huntsville, Alabama

I taught an introductory lab class at the University of

Alabama in Huntsville (UAH); I was responsible for

instructing two different classes of 15 undergrad/grad

college students, covering introductory VHDL principles.

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